2.0.18

What's New — CPU Backend Expansion

This release is a major expansion of the CPU backend, adding ~4 800 lines
of new benchmark kernels and probes across ISA-specific extensions for both
x86 and ARM.

New Benchmark Probes

Benchmark	Description
ComputeInt16DP	int16 dot-product throughput (x86 AVX-VNNI-INT16)
ComputeFP8DP	fp8 dot-product throughput (ARM FEAT_FP8DOT4)
ComputeDivSqrt	FP divide + sqrt throughput
ComputeIntDiv	Scalar u64 integer divide throughput
CryptoAes	AES-128 encrypt throughput (AES-NI / VAES-512 / ARM FEAT_AES)
CryptoSha256	SHA-256 compression throughput (SHA-NI / ARM FEAT_SHA256)
CryptoSha512	SHA-512 compression throughput (ARM FEAT_SHA512)
CryptoCrc32c	CRC32-C throughput (SSE4.2 CRC32 / ARM FEAT_CRC32)
StringScan	memchr-style SIMD byte scan, L1-resident (GB/s)
Utf8Validate	UTF-8 validation via lookup-shuffle PSHUFB/TBL (GB/s)
Atomics	Atomic fetch-add: uncontended / contended (ns)
BranchPenalty	Branch mispredict penalty (ns)

New Categories

• Category::Crypto — fixed-function crypto/hash silicon (AES, SHA, CRC)
• Category::String — string/text processing (byte scan, UTF-8 validation)

New ISA Extensions Supported

ARM:

• SVE / SVE2 fixed-function throughput
• SME / SME2 matrix engine probes
• FP8 dot-product (FEAT_FP8DOT4)
• MIDR_EL1 decode for ARM CPU names when no brand string exists
• Vendor name populated from MIDR implementer

x86:

• AVX-VNNI / AVX-VNNI-INT8
• AMX-FP16 / AMX-TF32 / AMX-FP8
• AVX10.2 bf16 FMA
• int16 dot-product (VPDPWSSD)

Enhancements

• NEON fp32/fp64/fp16 compute chains are now accumulator-destructive (prevents
  the compiler from folding the chain into a single multiply-accumulate).
• Memory latency probes now include MLP (memory-level parallelism), TLB reach,
  and branch-mispredict latency alongside the existing pointer-chase.
• CPU device detection expanded with microarch decoding, feature-flag
  enumeration, and ISA-dispatched kernel registry.

Bug Fixes

• Fix ARM CPU vendor string not being filled when a name already exists (#188).
• Don't emit x86-only AMX / AVX10.2 tests on ARM.
• Don't build SVE translation units on Windows (clang-cl can't mangle SVE types).
• Define NOMINMAX on Windows to prevent windows.h macro collisions.

Internal

• Refactor: removed CLPEAK_CPU_NATIVE_ARCH build flag; kernels are now
  modularized into per-feature header-only translation units under
  src/cpu/kernels/ and registered at compile time via cpu_tu_registry.h.
• Refactor: cpu_kernels_impl.h split into focused files (base_compute.h,
  sve_compute.h, sme_compute.h, lowp_compute.h, matrix_compute.h,
  crypto_compute.h, string_compute.h).

Full Changelog: 2.0.17...2.0.18