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Fix zero extension for MOVD semantics with MMX registers#764

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kyle-elliott-tob merged 1 commit intolifting-bits:masterfrom
momo5502:movdq-fix
Mar 11, 2026
Merged

Fix zero extension for MOVD semantics with MMX registers#764
kyle-elliott-tob merged 1 commit intolifting-bits:masterfrom
momo5502:movdq-fix

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https://www.felixcloutier.com/x86/movd:movq

When the destination operand is an MMX technology register, the source operand is written to the low doubleword of the register, and the register is zero-extended to 64 bits.

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I think due to an unintentional side affect this previously still worked on amd64 (V32W being RVnW<vec64_t>) but I know this was definitely wrong before for i386. Nice catch

@kyle-elliott-tob kyle-elliott-tob merged commit 962b68b into lifting-bits:master Mar 11, 2026
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@momo5502 momo5502 deleted the movdq-fix branch March 12, 2026 12:32
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2 participants