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QEMU TriCore AURIX v1.0.0: TC3x and TC4x SoC Emulation

QEMU TriCore AURIX v1.0.0: TC3x and TC4x SoC Emulation Latest
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@github-actions github-actions released this 17 Apr 20:01
v1.0.0
9e88819

QEMU emulation support for Infineon AURIX TriCore TC3x and TC4x microcontroller families, enabling Zephyr RTOS development and CI without hardware.

Based on upstream QEMU v11.0.0-rc4 (da6c4fe60fee).

Supported Machines

Machine SoC ISA Zephyr Board
KIT_AURIX_TC397B_TRB TC39XB (B-Step) TC1.6.2P qemu_tc3x
KIT_A3G_TC4D7_LITE TC4DX TC1.8P qemu_tc4x

KIT_AURIX_TC277_TRB (TC27XD) is also included but not tested. Use at your own risk.

Peripheral Models

  • Interrupt Router (tricore_ir): SRN-based interrupt controller with TC3x/TC4x SRC bit layout dispatch, PIPN/CCPN priority evaluation
  • ASCLIN UART: ASC mode with TX/RX FIFO, interrupt-driven operation, TC3x/TC4x register map variants
  • System Timer (STM): 64-bit free-running counter, CMP0/CMP1 compare match interrupts, dynamic clock update
  • System Control Unit (SCU): CCUCONx clock dividers, PMCSR idle/halt for k_cpu_idle()
  • TC4x Clock: PLL0/PLL1/PLL2, CCUCONx divider tree, fSPB/fSTM/fCPU derivation from external oscillator

ISA Extensions (over upstream TC1.3.1)

  • TC1.6.2P: RFH, 16-bit CALLI, tc37x/tc39x CPU models
  • TC1.8P: CMPSWAP.W, SWAPMSK.W, CRC32B.W, CRC32L.W, POPCNT.W, SHUFFLE, CLO.B/H, CLS.B/H, WAIT, DIV64/DIV64U, double-precision FPU (ADD.D, SUB.D, MUL.D, DIV.D, CMP.D, FTOD, DTOF, MADD/MSUB.D variants), tc4x CPU model

Key Fixes

  • MFCR/MTCR TCG global aliasing for ICR and PCXI (fixes arch_irq_lock within same translation block)
  • WAIT instruction stores correct return PC (pc_succ_insn) for interrupt resume
  • ISYNC deferred halt via pmcsr_sleep_pending (avoids blocked re-entrant I/O from MMIO context)
  • PCXI save uses bitwise OR for upper/lower context link field
  • DISABLE emits branch after helper call (prevents fall-through execution)
  • PCON/DCON CSFRs with auto-clear PCON1.PCINV

Validated Zephyr Samples (v4.4.0-rc3 + TriCore port)

  • samples/hello_world (with k_msleep)
  • samples/philosophers
  • tests/kernel/context (all 9 subtests including test_cpu_idle)
  • samples/posix/uname (with CONFIG_SHELL=y)
  • Min-heap sample

Usage

qemu-system-tricore -machine KIT_AURIX_TC397B_TRB -kernel zephyr.elf -nographic
qemu-system-tricore -machine KIT_A3G_TC4D7_LITE -kernel zephyr.elf -nographic

Issues

Report bugs at: https://github.com/linumiz/qemu-tricore/issues

Credits

  • Christoph Seitz (Infineon) -- TC4x clock, interrupt router rework, ISA 1.8 opcodes, double-precision FPU, CPU model refactoring
  • Andreas Konopik, David Brenken (EFS) -- original TC27x SoC, SCU, STM, ASCLIN foundations
  • Georg Hofstetter, Bastian Koppelmann -- paravirtualization device, early ASCLIN work

Contact:

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