firtool-1.160.0

What's Changed

• Bump LLVM by @uenoku in #11071
• [AXI4] Add concurrent read/write count to subordinate-like ops by @TaoBi22 in #11062
• [ImportVerilog] Support enum next, prev, name methods by @fabianschuiki in #11042
• [datapath] Lower Product of Sum to a Booth Encoded Partial Product Array by @cowardsa in #11039
• [AXI4] Add xbar op by @TaoBi22 in #10991
• [AXI4] Add verify-axi4-networks pass by @TaoBi22 in #11052
• [PyCDE] Fix the nightly "Test PyCDE and the ESI runtime" workflow by @teqdruid in #11103
• [MoreToCore] Add lowering for string comparison and case conversion methods by @ovdiiuv in #11088
• [ESI][Runtime] Dynamically allocate ChannelMMIO regions by @teqdruid in #11099
• [ESI] Propagate client options to engine hostmem sub-requests by @teqdruid in #11116
• [VerifyAXI4Networks] Warn on undersized xbar outstanding counts by @TaoBi22 in #11105
• [AXI4ToHW] Add lower-axi4-to-hw pass boilerplate by @TaoBi22 in #11108
• [SV] Add an sv.package operation by @teqdruid in #11100
• [Arc] Remove i0 state types in RemoveI0Types by @kevinyuan in #11113
• [FIRRTL][LOA] Preserve domains in open aggregates by @SawyDust1228 in #11119
• [ESI][Cosim] Enable Questa +acc only in debug mode by @teqdruid in #11127
• [Moore] Document x/z behaviour of logic_to_int by @TaoBi22 in #11126
• [ImportVerilog] Emit labeled concurrent assertions outside a procedure by @zarubaf in #11065
• [LLHD] Support UnionType in CombineDrives by @fabianschuiki in #11136
• [ESI][Cosim] Add command-line macro definitions by @teqdruid in #11137
• [ExportVerilog] Emit sv.package and package-qualified types by @teqdruid in #11101
• [Doc] Update the pass tutorial by @uenoku in #11138
• [ESI] Avoid resetting data paths by @teqdruid in #11140
• [ESI][Cosim] Add macro definition file support by @teqdruid in #11150
• [HWAggregateToComb] Add support for !hw.union by @fzi-hielscher in #11149
• [NFC][ImportVerilog] Clean up clang-tidy else-after-return complaints by @TaoBi22 in #11144
• [ESI] Run Verilator tests on Windows by @teqdruid in #11153
• [PyCDE] Pin nanobind build dependency by @teqdruid in #11156
• [ImportVerilog] Add support for three-stage buffers and inverters by @joaovam in #11089
• [NFC][ImportVerilog] Add three-state primitive error tests by @TaoBi22 in #11163
• [NFC][ImportVerilog] Drop a few unnecessary includes by @TaoBi22 in #11161
• [ImportVerilog] Error out on unsupported task call outputs by @TaoBi22 in #11167
• [ESI][Cosim] Order directory sources by ExportVerilog's filelist by @teqdruid in #11157
• [PyCDE] Emit type aliases in an sv.package by @teqdruid in #11158
• [Arcilator] Register LTL dialect by @fabianschuiki in #11168
• [CI] tweak python wheel building to limit parallelism, use lld. by @dtzSiFive in #11169

New Contributors

• @kevinyuan made their first contribution in #11113
• @SawyDust1228 made their first contribution in #11119
• @zarubaf made their first contribution in #11065

Full Changelog: firtool-1.159.0...firtool-1.160.0