firtool-1.161.0

What's Changed

• [Sim] Remove trailing whitespaces in SimOps.td, NFC by @fzi-hielscher in #11177
• [FIRRTL] Preserve register initial values in optimizer by @prithayan in #11069
• [SV] Add core !sv.net<T> and !sv.var<T> type support by @okekayode in #11154
• [PyCDE] TypeAlias should support as_bits()/bitcast (missing .width) by @teqdruid in #11174
• [FIRRTL] Parse static indexing after probe/rwprobe in ref expressions by @dtzSiFive in #11182
• [PyCDE] Forward type field lookup through aliases by @teqdruid in #11183
• [ImportVerilog] Add MOS switch primitive support by @mafeguimaraes in #11093
• [NFC][ImportVerilog] Clean up unnecessary insertion guards by @TaoBi22 in #11186
• [NFC][ImportVerilog] Add missing (C)MOS prim error tests by @TaoBi22 in #11191
• [FIRRTL] Lower SizeOfIntrinsicOp when optimizations are disabled by @AlexanderPortland in #11090
• [ESI] Expose bundled channel subelements to MLIR replacers by @teqdruid in #11201
• [HW] Recursively canonicalize type aliases with MLIR replacer by @teqdruid in #11202
• [PyCDE] Add recursive type alias canonicalization by @teqdruid in #11184
• [NFC][ImportVerilog] Drop unreachable MOS primitive input errors by @TaoBi22 in #11192
• [ImportVerilog] Refactor delayed prim assignment into shared helper by @TaoBi22 in #11188
• [AXI4] Add cut op by @TaoBi22 in #11146
• [AXI4] Add cdc op by @TaoBi22 in #11147
• [ImportVerilog] Fix lvalue conversion for output/inout/ref arguments by @fabianschuiki in #11033
• [SV] Add var op by @okekayode in #11185
• [CI] Use circt-bot token to kick off circt-tests runs by @fabianschuiki in #11206
• [ESI] ChannelArbiter: add wide_fanin timing structures by @teqdruid in #11155
• [ImportVerilog] Handle delays on (C)MOS primitives by @TaoBi22 in #11189
• [ImportVerilog] Drop unreachable tristate prim error by @TaoBi22 in #11164

Full Changelog: firtool-1.160.0...firtool-1.161.0