[AMDGPU][NFC] Add an optional DSE pass during CodeGenPrepare

[cmc-rep]

By default, the option is off for now.

[llvmbot]

@llvm/pr-subscribers-backend-amdgpu

Author: Gang Chen (cmc-rep)

Changes

---

Full diff: https://github.com/llvm/llvm-project/pull/172069.diff

1 Files Affected:

• (modified) llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp (+7)

diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index 8a831f7915882..b8b6d2427d7d0 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -104,6 +104,7 @@
 #include "llvm/Transforms/IPO/GlobalDCE.h"
 #include "llvm/Transforms/IPO/Internalize.h"
 #include "llvm/Transforms/Scalar.h"
+#include "llvm/Transforms/Scalar/DeadStoreElimination.h"
 #include "llvm/Transforms/Scalar/EarlyCSE.h"
 #include "llvm/Transforms/Scalar/FlattenCFG.h"
 #include "llvm/Transforms/Scalar/GVN.h"
@@ -1413,6 +1414,9 @@ void AMDGPUPassConfig::addCodeGenPrepare() {
     addPass(createAMDGPULowerKernelArgumentsPass());
 
   TargetPassConfig::addCodeGenPrepare();
+  // TODO: Remove DSE when LoadStoreVectorizer is enhanced to handle
+  // partially overlapping vector-stores.
+  addPass(createDeadStoreEliminationPass());
 
   if (isPassEnabled(EnableLoadStoreVectorizer))
     addPass(createLoadStoreVectorizerPass());
@@ -2183,6 +2187,9 @@ void AMDGPUCodeGenPassBuilder::addCodeGenPrepare(AddIRPass &addPass) const {
     addPass(AMDGPULowerKernelArgumentsPass(TM));
 
   Base::addCodeGenPrepare(addPass);
+  // TODO: Remove DSE when LoadStoreVectorizer is enhanced to handle
+  // partially overlapping vector-stores.
+  addPass(DSEPass());
 
   if (isPassEnabled(EnableLoadStoreVectorizer))
     addPass(LoadStoreVectorizerPass());

[arsenm]

This should have already happened in the middle end optimizer. This would also need a phase ordering test

[github-actions]

✅ With the latest revision this PR passed the C/C++ code formatter.

[cmc-rep]

This should have already happened in the middle end optimizer. This would also need a phase ordering test

I have made this extra DSE pass optional, and it is off by default. We need this downstream since we have added a major IR transform in the middle end optimizer that require extra DSE afterwards. I could add this downstream only. However, I feel that people may find it a useful option in some other cases.

[arsenm]

This is not NFC

[arsenm]

We need this downstream since we have added a major IR transform in the middle end optimizer that require extra DSE afterwards.

This sounds like it could use better placement. This must have a phase ordering test that shows its useful, so keep it with this transform

[cmc-rep]

Will add this downstream where I can come up a relevant test.