[AArch64][SDAG] Combine INSERT_VECTOR_ELT(undef, ) -> VECTOR_SPLAT #173005

gbossu · 2025-12-19T13:18:30Z

This is a stacked PR:

llvmbot · 2025-12-19T13:19:03Z

@llvm/pr-subscribers-backend-aarch64

Author: Gaëtan Bossu (gbossu)

Changes

Full diff: https://github.com/llvm/llvm-project/pull/173005.diff

2 Files Affected:

(modified) llvm/lib/Target/AArch64/AArch64ISelLowering.cpp (+11)
(modified) llvm/test/CodeGen/AArch64/sve-insert-element.ll (+35-152)

diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 837393b0cbdcd..8c56071c5527d 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -27792,6 +27792,17 @@ performInsertVectorEltCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
   if (SDValue Res = removeRedundantInsertVectorElt(N))
     return Res;
 
+  // Turn INSERT_VECTOR_ELT(undef, Elt, Idx) into SPLAT_VECTOR(Elt)
+  // Do not bother with inserts into lane 0 because there are patterns to select
+  // them using INSERT_SUBREG hsub/ssub/dsub.
+  SDLoc DL(N);
+  SDValue Vec = N->getOperand(0);
+  SDValue Elt = N->getOperand(1);
+  SDValue Idx = N->getOperand(2);
+  EVT VecVT = Vec.getValueType();
+  if (VecVT.isScalableVector() && Vec->isUndef() && !isNullConstant(Idx))
+    return DCI.DAG.getNode(ISD::SPLAT_VECTOR, DL, VecVT, Elt);
+
   return performPostLD1Combine(N, DCI, true);
 }
 
diff --git a/llvm/test/CodeGen/AArch64/sve-insert-element.ll b/llvm/test/CodeGen/AArch64/sve-insert-element.ll
index 5cc54929756ff..3e1289b499764 100644
--- a/llvm/test/CodeGen/AArch64/sve-insert-element.ll
+++ b/llvm/test/CodeGen/AArch64/sve-insert-element.ll
@@ -165,18 +165,12 @@ define <vscale x 16 x i8> @test_lanex_16xi8(<vscale x 16 x i8> %a, i32 %x) {
   ret <vscale x 16 x i8> %b
 }
 
-; TODO: Implement DAG combiner.
 ; INSERT_VECTOR_ELT(undef, ...) -> VECTOR_SPLAT
 
 define <vscale x 16 x i8> @test_lanex_16xi8_poison(i8 %e, i32 %x) {
 ; CHECK-LABEL: test_lanex_16xi8_poison:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    index z0.b, #0, #1
-; CHECK-NEXT:    mov w8, w1
-; CHECK-NEXT:    ptrue p0.b
-; CHECK-NEXT:    mov z1.b, w8
-; CHECK-NEXT:    cmpeq p0.b, p0/z, z0.b, z1.b
-; CHECK-NEXT:    mov z0.b, p0/m, w0
+; CHECK-NEXT:    mov z0.b, w0
 ; CHECK-NEXT:    ret
   %b = insertelement <vscale x 16 x i8> poison, i8 %e, i32 %x
   ret <vscale x 16 x i8> %b
@@ -185,13 +179,7 @@ define <vscale x 16 x i8> @test_lanex_16xi8_poison(i8 %e, i32 %x) {
 define <vscale x 16 x i8> @test_lanex_16xi8_poison_imm(i8 %e, i32 %x) {
 ; CHECK-LABEL: test_lanex_16xi8_poison_imm:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    index z0.b, #0, #1
-; CHECK-NEXT:    mov w8, w1
-; CHECK-NEXT:    ptrue p0.b
-; CHECK-NEXT:    mov z1.b, w8
-; CHECK-NEXT:    mov w8, #5 // =0x5
-; CHECK-NEXT:    cmpeq p0.b, p0/z, z0.b, z1.b
-; CHECK-NEXT:    mov z0.b, p0/m, w8
+; CHECK-NEXT:    mov z0.b, #5 // =0x5
 ; CHECK-NEXT:    ret
   %b = insertelement <vscale x 16 x i8> poison, i8 5, i32 %x
   ret <vscale x 16 x i8> %b
@@ -200,12 +188,7 @@ define <vscale x 16 x i8> @test_lanex_16xi8_poison_imm(i8 %e, i32 %x) {
 define <vscale x 8 x i16> @test_lanex_8xi16_poison(i16 %e, i32 %x) {
 ; CHECK-LABEL: test_lanex_8xi16_poison:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    index z0.h, #0, #1
-; CHECK-NEXT:    mov w8, w1
-; CHECK-NEXT:    ptrue p0.h
-; CHECK-NEXT:    mov z1.h, w8
-; CHECK-NEXT:    cmpeq p0.h, p0/z, z0.h, z1.h
-; CHECK-NEXT:    mov z0.h, p0/m, w0
+; CHECK-NEXT:    mov z0.h, w0
 ; CHECK-NEXT:    ret
   %b = insertelement <vscale x 8 x i16> poison, i16 %e, i32 %x
   ret <vscale x 8 x i16> %b
@@ -214,13 +197,7 @@ define <vscale x 8 x i16> @test_lanex_8xi16_poison(i16 %e, i32 %x) {
 define <vscale x 8 x i16> @test_lanex_8xi16_poison_imm(i32 %x) {
 ; CHECK-LABEL: test_lanex_8xi16_poison_imm:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    index z0.h, #0, #1
-; CHECK-NEXT:    mov w8, w0
-; CHECK-NEXT:    ptrue p0.h
-; CHECK-NEXT:    mov z1.h, w8
-; CHECK-NEXT:    mov w8, #5 // =0x5
-; CHECK-NEXT:    cmpeq p0.h, p0/z, z0.h, z1.h
-; CHECK-NEXT:    mov z0.h, p0/m, w8
+; CHECK-NEXT:    mov z0.h, #5 // =0x5
 ; CHECK-NEXT:    ret
   %b = insertelement <vscale x 8 x i16> poison, i16 5, i32 %x
   ret <vscale x 8 x i16> %b
@@ -229,12 +206,7 @@ define <vscale x 8 x i16> @test_lanex_8xi16_poison_imm(i32 %x) {
 define <vscale x 4 x i32> @test_lanex_4xi32_poison(i32 %e, i32 %x) {
 ; CHECK-LABEL: test_lanex_4xi32_poison:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    index z0.s, #0, #1
-; CHECK-NEXT:    mov w8, w1
-; CHECK-NEXT:    ptrue p0.s
-; CHECK-NEXT:    mov z1.s, w8
-; CHECK-NEXT:    cmpeq p0.s, p0/z, z0.s, z1.s
-; CHECK-NEXT:    mov z0.s, p0/m, w0
+; CHECK-NEXT:    mov z0.s, w0
 ; CHECK-NEXT:    ret
   %b = insertelement <vscale x 4 x i32> poison, i32 %e, i32 %x
   ret <vscale x 4 x i32> %b
@@ -243,13 +215,7 @@ define <vscale x 4 x i32> @test_lanex_4xi32_poison(i32 %e, i32 %x) {
 define <vscale x 4 x i32> @test_lanex_4xi32_poison_imm(i32 %x) {
 ; CHECK-LABEL: test_lanex_4xi32_poison_imm:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    index z0.s, #0, #1
-; CHECK-NEXT:    mov w8, w0
-; CHECK-NEXT:    ptrue p0.s
-; CHECK-NEXT:    mov z1.s, w8
-; CHECK-NEXT:    mov w8, #5 // =0x5
-; CHECK-NEXT:    cmpeq p0.s, p0/z, z0.s, z1.s
-; CHECK-NEXT:    mov z0.s, p0/m, w8
+; CHECK-NEXT:    mov z0.s, #5 // =0x5
 ; CHECK-NEXT:    ret
   %b = insertelement <vscale x 4 x i32> poison, i32 5, i32 %x
   ret <vscale x 4 x i32> %b
@@ -258,12 +224,7 @@ define <vscale x 4 x i32> @test_lanex_4xi32_poison_imm(i32 %x) {
 define <vscale x 2 x i64> @test_lanex_2xi64_poison(i64 %e, i32 %x) {
 ; CHECK-LABEL: test_lanex_2xi64_poison:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    index z0.d, #0, #1
-; CHECK-NEXT:    mov w8, w1
-; CHECK-NEXT:    ptrue p0.d
-; CHECK-NEXT:    mov z1.d, x8
-; CHECK-NEXT:    cmpeq p0.d, p0/z, z0.d, z1.d
-; CHECK-NEXT:    mov z0.d, p0/m, x0
+; CHECK-NEXT:    mov z0.d, x0
 ; CHECK-NEXT:    ret
   %b = insertelement <vscale x 2 x i64> poison, i64 %e, i32 %x
   ret <vscale x 2 x i64> %b
@@ -272,13 +233,7 @@ define <vscale x 2 x i64> @test_lanex_2xi64_poison(i64 %e, i32 %x) {
 define <vscale x 2 x i64> @test_lanex_2xi64_poison_imm(i32 %x) {
 ; CHECK-LABEL: test_lanex_2xi64_poison_imm:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    index z0.d, #0, #1
-; CHECK-NEXT:    mov w8, w0
-; CHECK-NEXT:    ptrue p0.d
-; CHECK-NEXT:    mov z1.d, x8
-; CHECK-NEXT:    mov w8, #5 // =0x5
-; CHECK-NEXT:    cmpeq p0.d, p0/z, z0.d, z1.d
-; CHECK-NEXT:    mov z0.d, p0/m, x8
+; CHECK-NEXT:    mov z0.d, #5 // =0x5
 ; CHECK-NEXT:    ret
   %b = insertelement <vscale x 2 x i64> poison, i64 5, i32 %x
   ret <vscale x 2 x i64> %b
@@ -287,11 +242,8 @@ define <vscale x 2 x i64> @test_lanex_2xi64_poison_imm(i32 %x) {
 define <vscale x 2 x half> @test_lanex_nxv2f16_poison(half %h, i64 %idx) {
 ; CHECK-LABEL: test_lanex_nxv2f16_poison:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    index z1.d, #0, #1
-; CHECK-NEXT:    mov z2.d, x0
-; CHECK-NEXT:    ptrue p0.d
-; CHECK-NEXT:    cmpeq p0.d, p0/z, z1.d, z2.d
-; CHECK-NEXT:    mov z0.h, p0/m, h0
+; CHECK-NEXT:    // kill: def $h0 killed $h0 def $z0
+; CHECK-NEXT:    mov z0.h, h0
 ; CHECK-NEXT:    ret
   %res = insertelement <vscale x 2 x half> poison, half %h, i64 %idx
   ret <vscale x 2 x half> %res
@@ -300,12 +252,7 @@ define <vscale x 2 x half> @test_lanex_nxv2f16_poison(half %h, i64 %idx) {
 define <vscale x 2 x half> @test_lanex_nxv2f16_poison_imm(i64 %idx) {
 ; CHECK-LABEL: test_lanex_nxv2f16_poison_imm:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    index z0.d, #0, #1
-; CHECK-NEXT:    mov z1.d, x0
-; CHECK-NEXT:    ptrue p0.d
-; CHECK-NEXT:    cmpeq p0.d, p0/z, z0.d, z1.d
-; CHECK-NEXT:    fmov h0, #1.50000000
-; CHECK-NEXT:    mov z0.h, p0/m, h0
+; CHECK-NEXT:    fmov z0.h, #1.50000000
 ; CHECK-NEXT:    ret
   %res = insertelement <vscale x 2 x half> poison, half 1.5, i64 %idx
   ret <vscale x 2 x half> %res
@@ -314,11 +261,8 @@ define <vscale x 2 x half> @test_lanex_nxv2f16_poison_imm(i64 %idx) {
 define <vscale x 4 x half> @test_lanex_nxv4f16_poison(half %h, i64 %idx) {
 ; CHECK-LABEL: test_lanex_nxv4f16_poison:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    index z1.s, #0, #1
-; CHECK-NEXT:    mov z2.s, w0
-; CHECK-NEXT:    ptrue p0.s
-; CHECK-NEXT:    cmpeq p0.s, p0/z, z1.s, z2.s
-; CHECK-NEXT:    mov z0.h, p0/m, h0
+; CHECK-NEXT:    // kill: def $h0 killed $h0 def $z0
+; CHECK-NEXT:    mov z0.h, h0
 ; CHECK-NEXT:    ret
   %res = insertelement <vscale x 4 x half> poison, half %h, i64 %idx
   ret <vscale x 4 x half> %res
@@ -327,12 +271,7 @@ define <vscale x 4 x half> @test_lanex_nxv4f16_poison(half %h, i64 %idx) {
 define <vscale x 4 x half> @test_lanex_nxv4f16_poison_imm(i64 %idx) {
 ; CHECK-LABEL: test_lanex_nxv4f16_poison_imm:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    index z0.s, #0, #1
-; CHECK-NEXT:    mov z1.s, w0
-; CHECK-NEXT:    ptrue p0.s
-; CHECK-NEXT:    cmpeq p0.s, p0/z, z0.s, z1.s
-; CHECK-NEXT:    fmov h0, #1.50000000
-; CHECK-NEXT:    mov z0.h, p0/m, h0
+; CHECK-NEXT:    fmov z0.h, #1.50000000
 ; CHECK-NEXT:    ret
   %res = insertelement <vscale x 4 x half> poison, half 1.5, i64 %idx
   ret <vscale x 4 x half> %res
@@ -341,11 +280,8 @@ define <vscale x 4 x half> @test_lanex_nxv4f16_poison_imm(i64 %idx) {
 define <vscale x 8 x half> @test_lanex_nxv8f16_poison(half %h, i64 %idx) {
 ; CHECK-LABEL: test_lanex_nxv8f16_poison:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    index z1.h, #0, #1
-; CHECK-NEXT:    mov z2.h, w0
-; CHECK-NEXT:    ptrue p0.h
-; CHECK-NEXT:    cmpeq p0.h, p0/z, z1.h, z2.h
-; CHECK-NEXT:    mov z0.h, p0/m, h0
+; CHECK-NEXT:    // kill: def $h0 killed $h0 def $z0
+; CHECK-NEXT:    mov z0.h, h0
 ; CHECK-NEXT:    ret
   %res = insertelement <vscale x 8 x half> poison, half %h, i64 %idx
   ret <vscale x 8 x half> %res
@@ -354,12 +290,7 @@ define <vscale x 8 x half> @test_lanex_nxv8f16_poison(half %h, i64 %idx) {
 define <vscale x 8 x half> @test_lanex_nxv8f16_poison_imm(i64 %idx) {
 ; CHECK-LABEL: test_lanex_nxv8f16_poison_imm:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    index z0.h, #0, #1
-; CHECK-NEXT:    mov z1.h, w0
-; CHECK-NEXT:    ptrue p0.h
-; CHECK-NEXT:    cmpeq p0.h, p0/z, z0.h, z1.h
-; CHECK-NEXT:    fmov h0, #1.50000000
-; CHECK-NEXT:    mov z0.h, p0/m, h0
+; CHECK-NEXT:    fmov z0.h, #1.50000000
 ; CHECK-NEXT:    ret
   %res = insertelement <vscale x 8 x half> poison, half 1.5, i64 %idx
   ret <vscale x 8 x half> %res
@@ -368,11 +299,8 @@ define <vscale x 8 x half> @test_lanex_nxv8f16_poison_imm(i64 %idx) {
 define <vscale x 2 x bfloat> @test_lanex_nxv2bf16_undef(bfloat %h, i64 %idx) {
 ; CHECK-LABEL: test_lanex_nxv2bf16_undef:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    index z1.d, #0, #1
-; CHECK-NEXT:    mov z2.d, x0
-; CHECK-NEXT:    ptrue p0.d
-; CHECK-NEXT:    cmpeq p0.d, p0/z, z1.d, z2.d
-; CHECK-NEXT:    mov z0.h, p0/m, h0
+; CHECK-NEXT:    // kill: def $h0 killed $h0 def $z0
+; CHECK-NEXT:    mov z0.h, h0
 ; CHECK-NEXT:    ret
   %res = insertelement <vscale x 2 x bfloat> poison, bfloat %h, i64 %idx
   ret <vscale x 2 x bfloat> %res
@@ -381,12 +309,7 @@ define <vscale x 2 x bfloat> @test_lanex_nxv2bf16_undef(bfloat %h, i64 %idx) {
 define <vscale x 2 x bfloat> @test_lanex_nxv2bf16_undef_imm(i64 %idx) {
 ; CHECK-LABEL: test_lanex_nxv2bf16_undef_imm:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    index z0.d, #0, #1
-; CHECK-NEXT:    mov z1.d, x0
-; CHECK-NEXT:    ptrue p0.d
-; CHECK-NEXT:    cmpeq p0.d, p0/z, z0.d, z1.d
-; CHECK-NEXT:    fmov h0, #1.93750000
-; CHECK-NEXT:    mov z0.h, p0/m, h0
+; CHECK-NEXT:    fmov z0.h, #1.93750000
 ; CHECK-NEXT:    ret
   %res = insertelement <vscale x 2 x bfloat> poison, bfloat 1.5, i64 %idx
   ret <vscale x 2 x bfloat> %res
@@ -395,11 +318,8 @@ define <vscale x 2 x bfloat> @test_lanex_nxv2bf16_undef_imm(i64 %idx) {
 define <vscale x 4 x bfloat> @test_lanex_nxv4bf16_undef(bfloat %h, i64 %idx) {
 ; CHECK-LABEL: test_lanex_nxv4bf16_undef:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    index z1.s, #0, #1
-; CHECK-NEXT:    mov z2.s, w0
-; CHECK-NEXT:    ptrue p0.s
-; CHECK-NEXT:    cmpeq p0.s, p0/z, z1.s, z2.s
-; CHECK-NEXT:    mov z0.h, p0/m, h0
+; CHECK-NEXT:    // kill: def $h0 killed $h0 def $z0
+; CHECK-NEXT:    mov z0.h, h0
 ; CHECK-NEXT:    ret
   %res = insertelement <vscale x 4 x bfloat> poison, bfloat %h, i64 %idx
   ret <vscale x 4 x bfloat> %res
@@ -408,12 +328,7 @@ define <vscale x 4 x bfloat> @test_lanex_nxv4bf16_undef(bfloat %h, i64 %idx) {
 define <vscale x 4 x bfloat> @test_lanex_nxv4bf16_undef_imm(i64 %idx) {
 ; CHECK-LABEL: test_lanex_nxv4bf16_undef_imm:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    index z0.s, #0, #1
-; CHECK-NEXT:    mov z1.s, w0
-; CHECK-NEXT:    ptrue p0.s
-; CHECK-NEXT:    cmpeq p0.s, p0/z, z0.s, z1.s
-; CHECK-NEXT:    fmov h0, #1.93750000
-; CHECK-NEXT:    mov z0.h, p0/m, h0
+; CHECK-NEXT:    fmov z0.h, #1.93750000
 ; CHECK-NEXT:    ret
   %res = insertelement <vscale x 4 x bfloat> poison, bfloat 1.5, i64 %idx
   ret <vscale x 4 x bfloat> %res
@@ -422,11 +337,8 @@ define <vscale x 4 x bfloat> @test_lanex_nxv4bf16_undef_imm(i64 %idx) {
 define <vscale x 8 x bfloat> @test_lanex_nxv8bf16_poison(bfloat %h, i64 %idx) {
 ; CHECK-LABEL: test_lanex_nxv8bf16_poison:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    index z1.h, #0, #1
-; CHECK-NEXT:    mov z2.h, w0
-; CHECK-NEXT:    ptrue p0.h
-; CHECK-NEXT:    cmpeq p0.h, p0/z, z1.h, z2.h
-; CHECK-NEXT:    mov z0.h, p0/m, h0
+; CHECK-NEXT:    // kill: def $h0 killed $h0 def $z0
+; CHECK-NEXT:    mov z0.h, h0
 ; CHECK-NEXT:    ret
   %res = insertelement <vscale x 8 x bfloat> poison, bfloat %h, i64 %idx
   ret <vscale x 8 x bfloat> %res
@@ -435,12 +347,7 @@ define <vscale x 8 x bfloat> @test_lanex_nxv8bf16_poison(bfloat %h, i64 %idx) {
 define <vscale x 8 x bfloat> @test_lanex_nxv8bf16_poison_imm(i64 %idx) {
 ; CHECK-LABEL: test_lanex_nxv8bf16_poison_imm:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    index z0.h, #0, #1
-; CHECK-NEXT:    mov z1.h, w0
-; CHECK-NEXT:    ptrue p0.h
-; CHECK-NEXT:    cmpeq p0.h, p0/z, z0.h, z1.h
-; CHECK-NEXT:    fmov h0, #1.93750000
-; CHECK-NEXT:    mov z0.h, p0/m, h0
+; CHECK-NEXT:    fmov z0.h, #1.93750000
 ; CHECK-NEXT:    ret
   %res = insertelement <vscale x 8 x bfloat> poison, bfloat 1.5, i64 %idx
   ret <vscale x 8 x bfloat> %res
@@ -449,11 +356,8 @@ define <vscale x 8 x bfloat> @test_lanex_nxv8bf16_poison_imm(i64 %idx) {
 define <vscale x 2 x float> @test_lanex_nxv2f32_poison(float %f, i64 %idx) {
 ; CHECK-LABEL: test_lanex_nxv2f32_poison:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    index z1.d, #0, #1
-; CHECK-NEXT:    mov z2.d, x0
-; CHECK-NEXT:    ptrue p0.d
-; CHECK-NEXT:    cmpeq p0.d, p0/z, z1.d, z2.d
-; CHECK-NEXT:    mov z0.s, p0/m, s0
+; CHECK-NEXT:    // kill: def $s0 killed $s0 def $z0
+; CHECK-NEXT:    mov z0.s, s0
 ; CHECK-NEXT:    ret
   %res = insertelement <vscale x 2 x float> poison, float %f, i64 %idx
   ret <vscale x 2 x float> %res
@@ -462,12 +366,7 @@ define <vscale x 2 x float> @test_lanex_nxv2f32_poison(float %f, i64 %idx) {
 define <vscale x 2 x float> @test_lanex_nxv2f32_poison_imm(i64 %idx) {
 ; CHECK-LABEL: test_lanex_nxv2f32_poison_imm:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    index z0.d, #0, #1
-; CHECK-NEXT:    mov z1.d, x0
-; CHECK-NEXT:    ptrue p0.d
-; CHECK-NEXT:    cmpeq p0.d, p0/z, z0.d, z1.d
-; CHECK-NEXT:    fmov s0, #1.50000000
-; CHECK-NEXT:    mov z0.s, p0/m, s0
+; CHECK-NEXT:    fmov z0.s, #1.50000000
 ; CHECK-NEXT:    ret
   %res = insertelement <vscale x 2 x float> poison, float 1.5, i64 %idx
   ret <vscale x 2 x float> %res
@@ -476,11 +375,8 @@ define <vscale x 2 x float> @test_lanex_nxv2f32_poison_imm(i64 %idx) {
 define <vscale x 4 x float> @test_lanex_nxv4f32_poison(float %f, i64 %idx) {
 ; CHECK-LABEL: test_lanex_nxv4f32_poison:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    index z1.s, #0, #1
-; CHECK-NEXT:    mov z2.s, w0
-; CHECK-NEXT:    ptrue p0.s
-; CHECK-NEXT:    cmpeq p0.s, p0/z, z1.s, z2.s
-; CHECK-NEXT:    mov z0.s, p0/m, s0
+; CHECK-NEXT:    // kill: def $s0 killed $s0 def $z0
+; CHECK-NEXT:    mov z0.s, s0
 ; CHECK-NEXT:    ret
   %res = insertelement <vscale x 4 x float> poison, float %f, i64 %idx
   ret <vscale x 4 x float> %res
@@ -489,12 +385,7 @@ define <vscale x 4 x float> @test_lanex_nxv4f32_poison(float %f, i64 %idx) {
 define <vscale x 4 x float> @test_lanex_nxv4f32_poison_imm(float %f, i64 %idx) {
 ; CHECK-LABEL: test_lanex_nxv4f32_poison_imm:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    index z0.s, #0, #1
-; CHECK-NEXT:    mov z1.s, w0
-; CHECK-NEXT:    ptrue p0.s
-; CHECK-NEXT:    cmpeq p0.s, p0/z, z0.s, z1.s
-; CHECK-NEXT:    fmov s0, #1.50000000
-; CHECK-NEXT:    mov z0.s, p0/m, s0
+; CHECK-NEXT:    fmov z0.s, #1.50000000
 ; CHECK-NEXT:    ret
   %res = insertelement <vscale x 4 x float> poison, float 1.5, i64 %idx
   ret <vscale x 4 x float> %res
@@ -503,11 +394,8 @@ define <vscale x 4 x float> @test_lanex_nxv4f32_poison_imm(float %f, i64 %idx) {
 define <vscale x 2 x double> @test_lanex_nxv2f64_poison(double %d, i64 %idx) {
 ; CHECK-LABEL: test_lanex_nxv2f64_poison:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    index z1.d, #0, #1
-; CHECK-NEXT:    mov z2.d, x0
-; CHECK-NEXT:    ptrue p0.d
-; CHECK-NEXT:    cmpeq p0.d, p0/z, z1.d, z2.d
-; CHECK-NEXT:    mov z0.d, p0/m, d0
+; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
+; CHECK-NEXT:    mov z0.d, d0
 ; CHECK-NEXT:    ret
   %res = insertelement <vscale x 2 x double> poison, double %d, i64 %idx
   ret <vscale x 2 x double> %res
@@ -516,12 +404,7 @@ define <vscale x 2 x double> @test_lanex_nxv2f64_poison(double %d, i64 %idx) {
 define <vscale x 2 x double> @test_lanex_nxv2f64_poison_imm(i64 %idx) {
 ; CHECK-LABEL: test_lanex_nxv2f64_poison_imm:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    index z0.d, #0, #1
-; CHECK-NEXT:    mov z1.d, x0
-; CHECK-NEXT:    ptrue p0.d
-; CHECK-NEXT:    cmpeq p0.d, p0/z, z0.d, z1.d
-; CHECK-NEXT:    fmov d0, #1.50000000
-; CHECK-NEXT:    mov z0.d, p0/m, d0
+; CHECK-NEXT:    fmov z0.d, #1.50000000
 ; CHECK-NEXT:    ret
   %res = insertelement <vscale x 2 x double> poison, double 1.5, i64 %idx
   ret <vscale x 2 x double> %res

gbossu · 2025-12-19T13:35:42Z

llvm/test/CodeGen/AArch64/sve-insert-element.ll

-; CHECK-NEXT:    mov w8, #5 // =0x5
-; CHECK-NEXT:    cmpeq p0.b, p0/z, z0.b, z1.b
-; CHECK-NEXT:    mov z0.b, p0/m, w8
+; CHECK-NEXT:    mov z0.b, #5 // =0x5


Note that I haven't checked the immediate range, as I feel this should be tested in the SPLAT_VECTOR tests. Tbh this would be great to test the DAGCombiner independently of ISel patterns, but I don't think SDAG allows such fine-grained testing (unlike GlobalISel)

llvm-ci · 2025-12-19T17:56:51Z

LLVM Buildbot has detected a new failure on builder llvm-clang-x86_64-sie-ubuntu-fast running on sie-linux-worker while building llvm at step 6 "test-build-unified-tree-check-all".

Full details are available at: https://lab.llvm.org/buildbot/#/builders/144/builds/42692

Here is the relevant piece of the build log for the reference

Step 6 (test-build-unified-tree-check-all) failure: test (failure)
******************** TEST 'Clang :: Preprocessor/c99-6_10_3_4_p6.c' FAILED ********************
Exit Code: 1

Command Output (stdout):
--
# RUN: at line 3
/home/buildbot/buildbot-root/llvm-clang-x86_64-sie-ubuntu-fast/build/bin/clang -cc1 -internal-isystem /home/buildbot/buildbot-root/llvm-clang-x86_64-sie-ubuntu-fast/build/lib/clang/22/include -nostdsysteminc -E /home/buildbot/buildbot-root/llvm-clang-x86_64-sie-ubuntu-fast/llvm-project/clang/test/Preprocessor/c99-6_10_3_4_p6.c | /home/buildbot/buildbot-root/llvm-clang-x86_64-sie-ubuntu-fast/build/bin/FileCheck -strict-whitespace /home/buildbot/buildbot-root/llvm-clang-x86_64-sie-ubuntu-fast/llvm-project/clang/test/Preprocessor/c99-6_10_3_4_p6.c
# executed command: /home/buildbot/buildbot-root/llvm-clang-x86_64-sie-ubuntu-fast/build/bin/clang -cc1 -internal-isystem /home/buildbot/buildbot-root/llvm-clang-x86_64-sie-ubuntu-fast/build/lib/clang/22/include -nostdsysteminc -E /home/buildbot/buildbot-root/llvm-clang-x86_64-sie-ubuntu-fast/llvm-project/clang/test/Preprocessor/c99-6_10_3_4_p6.c
# .---command stderr------------
# | /home/buildbot/buildbot-root/llvm-clang-x86_64-sie-ubuntu-fast/llvm-project/clang/test/Preprocessor/c99-6_10_3_4_p6.c:7:57: warning: backslash and newline separated by space [-Wbackslash-newline-escape]
# |     7 | #define debug(s, t) printf("x" # s "= %d, x" # t "= s" \ 
# |       |                                                         ^
# | 1 warning generated.
# `-----------------------------
# executed command: /home/buildbot/buildbot-root/llvm-clang-x86_64-sie-ubuntu-fast/build/bin/FileCheck -strict-whitespace /home/buildbot/buildbot-root/llvm-clang-x86_64-sie-ubuntu-fast/llvm-project/clang/test/Preprocessor/c99-6_10_3_4_p6.c
# .---command stderr------------
# | �[1m/home/buildbot/buildbot-root/llvm-clang-x86_64-sie-ubuntu-fast/llvm-project/clang/test/Preprocessor/c99-6_10_3_4_p6.c:24:11: �[0m�[0;1;31merror: �[0m�[1mCHECK: expected string not found in input
�[0m# | �[1m�[0m// CHECK: include "vers2.h"
# | �[0;1;32m          ^
�[0m# | �[0;1;32m�[0m�[1m<stdin>:10:62: �[0m�[0;1;30mnote: �[0m�[1mscanning from here
�[0m# | �[1m�[0mfputs("strncmp(\"abc\\0d\" \"abc\", '\\4') == 0" ": @\n", s);
# | �[0;1;32m                                                             ^
�[0m# | �[0;1;32m�[0m�[1m<stdin>:12:1: �[0m�[0;1;30mnote: �[0m�[1mpossible intended match here
�[0m# | �[1m�[0minclude "vers2 .h"
# | �[0;1;32m^
�[0m# | �[0;1;32m�[0m
# | Input file: <stdin>
# | Check file: /home/buildbot/buildbot-root/llvm-clang-x86_64-sie-ubuntu-fast/llvm-project/clang/test/Preprocessor/c99-6_10_3_4_p6.c
# | 
# | -dump-input=help explains the following input dump.
# | 
# | Input was:
# | <<<<<<
# | �[1m�[0m�[0;1;30m            1: �[0m�[1m�[0;1;46m# 1 "/home/buildbot/buildbot-root/llvm-clang-x86_64-sie-ubuntu-fast/llvm-project/clang/test/Preprocessor/c99-6_10_3_4_p6.c" �[0m
# | �[0;1;30m            2: �[0m�[1m�[0;1;46m# 1 "<built-in>" 1 �[0m
# | �[0;1;30m            3: �[0m�[1m�[0;1;46m# 1 "<built-in>" 3 �[0m
# | �[0;1;30m            4: �[0m�[1m�[0;1;46m# 389 "<built-in>" 3 �[0m
# | �[0;1;30m            5: �[0m�[1m�[0;1;46m# 1 "<command line>" 1 �[0m
# | �[0;1;30m            6: �[0m�[1m�[0;1;46m# 1 "<built-in>" 2 �[0m
# | �[0;1;30m            7: �[0m�[1m�[0;1;46m# 1 "/home/buildbot/buildbot-root/llvm-clang-x86_64-sie-ubuntu-fast/llvm-project/clang/test/Preprocessor/c99-6_10_3_4_p6.c" 2 �[0m
# | �[0;1;30m            8: �[0m�[1m�[0;1;46m# 14 "/home/buildbot/buildbot-root/llvm-clang-x86_64-sie-ubuntu-fast/llvm-project/clang/test/Preprocessor/c99-6_10_3_4_p6.c" �[0m
# | �[0;1;30m            9: �[0m�[1m�[0;1;46m�[0mprintf("x" "1" "= %d, x" "2" "= s" x1, x2);�[0;1;46m �[0m
# | �[0;1;32mcheck:22       ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
�[0m# | �[0;1;32m�[0m�[0;1;30m           10: �[0m�[1m�[0;1;46m�[0mfputs("strncmp(\"abc\\0d\" \"abc\", '\\4') == 0" ": @\n", s);�[0;1;46m �[0m
# | �[0;1;32mcheck:23       ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
�[0m# | �[0;1;32m�[0m�[0;1;31mcheck:24'0                                                                  X error: no match found
�[0m# | �[0;1;31m�[0m�[0;1;30m           11: �[0m�[1m�[0;1;46m �[0m
# | �[0;1;31mcheck:24'0     ~
�[0m# | �[0;1;31m�[0m�[0;1;30m           12: �[0m�[1m�[0;1;46minclude "vers2 .h" �[0m
# | �[0;1;31mcheck:24'0     ~~~~~~~~~~~~~~~~~~~
...

llvmbot added the backend:AArch64 label Dec 19, 2025

gbossu mentioned this pull request Dec 19, 2025

[AArch64][ISel] Extend insertelement tests #173003

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gbossu force-pushed the users/gbossu/gbossu.insert.into.undef.2 branch from b361673 to 10ad8b3 Compare December 19, 2025 13:30

gbossu commented Dec 19, 2025

View reviewed changes

gbossu requested review from MacDue, paulwalker-arm and sdesmalen-arm December 19, 2025 13:36

sdesmalen-arm approved these changes Dec 19, 2025

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gbossu force-pushed the users/gbossu/gbossu.insert.into.undef.2 branch from 10ad8b3 to 219565c Compare December 19, 2025 15:10

Base automatically changed from users/gbossu/gbossu.insert.into.undef.1 to main December 19, 2025 16:30

[AArch64][SDAG] Combine INSERT_VECTOR_ELT(undef, ) -> VECTOR_SPLAT

bdf160b

gbossu force-pushed the users/gbossu/gbossu.insert.into.undef.2 branch from 219565c to bdf160b Compare December 19, 2025 16:33

gbossu merged commit 11d4de8 into main Dec 19, 2025
10 checks passed

gbossu deleted the users/gbossu/gbossu.insert.into.undef.2 branch December 19, 2025 17:26

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[AArch64][SDAG] Combine INSERT_VECTOR_ELT(undef, ) -> VECTOR_SPLAT #173005

[AArch64][SDAG] Combine INSERT_VECTOR_ELT(undef, ) -> VECTOR_SPLAT #173005

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[AArch64][SDAG] Combine INSERT_VECTOR_ELT(undef, ) -> VECTOR_SPLAT #173005

[AArch64][SDAG] Combine INSERT_VECTOR_ELT(undef, ) -> VECTOR_SPLAT #173005

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