[GlobalISel] Add known-bits for G_INSERT_VECTOR_ELT.

[davemgreen]

Mostly a copy of the SDAG equivalent code.

[llvmorg-github-actions]

@llvm/pr-subscribers-llvm-globalisel

@llvm/pr-subscribers-backend-aarch64

Author: David Green (davemgreen)

Changes

Mostly a copy of the SDAG equivalent code.

---

Full diff: https://github.com/llvm/llvm-project/pull/200930.diff

2 Files Affected:

• (modified) llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp (+30)
• (added) llvm/test/CodeGen/AArch64/GlobalISel/knownbits-insert-vector.mir (+81)

diff --git a/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp b/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
index ea4ab73700cf0..bf8d5e9fde619 100644
--- a/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
@@ -870,6 +870,36 @@ void GISelValueTracking::computeKnownBitsImpl(Register R, KnownBits &Known,
     computeKnownBitsImpl(InVec, Known, DemandedSrcElts, Depth + 1);
     break;
   }
+  case TargetOpcode::G_INSERT_VECTOR_ELT: {
+    GInsertVectorElement &Insert = cast<GInsertVectorElement>(MI);
+    Register InVec = Insert.getVectorReg();
+    Register InVal = Insert.getElementReg();
+    Register EltNo = Insert.getIndexReg();
+    LLT VecVT = MRI.getType(InVec);
+
+    if (VecVT.isScalableVector())
+      break;
+
+    auto ConstEltNo = getIConstantVRegVal(EltNo, MRI);
+
+    bool DemandedVal = true;
+    APInt DemandedVecElts = DemandedElts;
+    if (ConstEltNo) {
+      unsigned EltIdx = ConstEltNo->getZExtValue();
+      DemandedVal = !!DemandedElts[EltIdx];
+      DemandedVecElts.clearBit(EltIdx);
+    }
+    Known.setAllConflict();
+    if (DemandedVal) {
+      computeKnownBitsImpl(InVal, Known2, APInt(1, 1), Depth + 1);
+      Known = Known.intersectWith(Known2.zextOrTrunc(BitWidth));
+    }
+    if (!!DemandedVecElts) {
+      computeKnownBitsImpl(InVec, Known2, DemandedVecElts, Depth + 1);
+      Known = Known.intersectWith(Known2);
+    }
+    break;
+  }
   case TargetOpcode::G_SHUFFLE_VECTOR: {
     APInt DemandedLHS, DemandedRHS;
     // Collect the known bits that are shared by every vector element referenced
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-insert-vector.mir b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-insert-vector.mir
new file mode 100644
index 0000000000000..a148f301bfadf
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-insert-vector.mir
@@ -0,0 +1,81 @@
+# NOTE: Assertions have been autogenerated by utils/update_givaluetracking_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -mtriple aarch64 -passes="print<gisel-value-tracking>" %s -filetype=null 2>&1 | FileCheck %s
+
+---
+name: all_knownbits_const_idx
+body: |
+  bb.0:
+  ; CHECK-LABEL: name: @all_knownbits_const_idx
+  ; CHECK-NEXT: %idx:_ KnownBits:0000000000000000000000000000000000000000000000000000000000000001 SignBits:63
+  ; CHECK-NEXT: %1:_ KnownBits:00000011 SignBits:6
+  ; CHECK-NEXT: %2:_ KnownBits:00001111 SignBits:4
+  ; CHECK-NEXT: %3:_ KnownBits:0000??11 SignBits:4
+  ; CHECK-NEXT: %4:_ KnownBits:00000110 SignBits:5
+  ; CHECK-NEXT: %5:_ KnownBits:00000?1? SignBits:5
+    %idx:_(i64) = G_CONSTANT i64 1
+    %0:_(i8) = G_CONSTANT i8 3
+    %1:_(i8) = G_CONSTANT i8 15
+    %2:_(<2 x i8>) = G_BUILD_VECTOR %0, %1
+    %3:_(i8) = G_CONSTANT i8 6
+    %4:_(<2 x i8>) = G_INSERT_VECTOR_ELT %2, %3, %idx
+...
+---
+name: all_knownbits_unknown_lane
+body: |
+  bb.0:
+  ; CHECK-LABEL: name: @all_knownbits_unknown_lane
+  ; CHECK-NEXT: %idx:_ KnownBits:???????????????????????????????????????????????????????????????? SignBits:1
+  ; CHECK-NEXT: %1:_ KnownBits:00000011 SignBits:6
+  ; CHECK-NEXT: %2:_ KnownBits:00001111 SignBits:4
+  ; CHECK-NEXT: %3:_ KnownBits:0000??11 SignBits:4
+  ; CHECK-NEXT: %4:_ KnownBits:00000110 SignBits:5
+  ; CHECK-NEXT: %5:_ KnownBits:0000??1? SignBits:4
+    %idx:_(i64) = COPY $x0
+    %0:_(i8) = G_CONSTANT i8 3
+    %1:_(i8) = G_CONSTANT i8 15
+    %2:_(<2 x i8>) = G_BUILD_VECTOR %0, %1
+    %3:_(i8) = G_CONSTANT i8 6
+    %4:_(<2 x i8>) = G_INSERT_VECTOR_ELT %2, %3, %idx
+...
+---
+name: all_knownbits_const_idx_demand_0
+body: |
+  bb.0:
+  ; CHECK-LABEL: name: @all_knownbits_const_idx_demand_0
+  ; CHECK-NEXT: %idx0:_ KnownBits:0000000000000000000000000000000000000000000000000000000000000000 SignBits:64
+  ; CHECK-NEXT: %1:_ KnownBits:00000011 SignBits:6
+  ; CHECK-NEXT: %2:_ KnownBits:00001111 SignBits:4
+  ; CHECK-NEXT: %3:_ KnownBits:0000??11 SignBits:4
+  ; CHECK-NEXT: %4:_ KnownBits:00000110 SignBits:5
+  ; CHECK-NEXT: %5:_ KnownBits:0000?11? SignBits:4
+  ; CHECK-NEXT: %6:_ KnownBits:00000110 SignBits:5
+    %idx0:_(i64) = G_CONSTANT i64 0
+    %0:_(i8) = G_CONSTANT i8 3
+    %1:_(i8) = G_CONSTANT i8 15
+    %2:_(<2 x i8>) = G_BUILD_VECTOR %0, %1
+    %3:_(i8) = G_CONSTANT i8 6
+    %4:_(<2 x i8>) = G_INSERT_VECTOR_ELT %2, %3, %idx0
+    %5:_(i8) = G_EXTRACT_VECTOR_ELT %4, %idx0
+...
+---
+name: all_knownbits_const_idx_demand_1
+body: |
+  bb.0:
+  ; CHECK-LABEL: name: @all_knownbits_const_idx_demand_1
+  ; CHECK-NEXT: %idx0:_ KnownBits:0000000000000000000000000000000000000000000000000000000000000000 SignBits:64
+  ; CHECK-NEXT: %idx1:_ KnownBits:0000000000000000000000000000000000000000000000000000000000000001 SignBits:63
+  ; CHECK-NEXT: %2:_ KnownBits:00000011 SignBits:6
+  ; CHECK-NEXT: %3:_ KnownBits:00001111 SignBits:4
+  ; CHECK-NEXT: %4:_ KnownBits:0000??11 SignBits:4
+  ; CHECK-NEXT: %5:_ KnownBits:00000110 SignBits:5
+  ; CHECK-NEXT: %6:_ KnownBits:0000?11? SignBits:4
+  ; CHECK-NEXT: %7:_ KnownBits:00001111 SignBits:4
+    %idx0:_(i64) = G_CONSTANT i64 0
+    %idx1:_(i64) = G_CONSTANT i64 1
+    %0:_(i8) = G_CONSTANT i8 3
+    %1:_(i8) = G_CONSTANT i8 15
+    %2:_(<2 x i8>) = G_BUILD_VECTOR %0, %1
+    %3:_(i8) = G_CONSTANT i8 6
+    %4:_(<2 x i8>) = G_INSERT_VECTOR_ELT %2, %3, %idx0
+    %5:_(i8) = G_EXTRACT_VECTOR_ELT %4, %idx1
+...

[AZero13]

It in fact matches the DAG version.

[c-rhodes]

LGTM cheers