[RISCV] Implement Zicfiss Extension Bitmask

[lenary]

This implements the proposal here: riscv-non-isa/riscv-c-api-doc#187

This was prepared with the assistance of AI.

[llvmorg-github-actions]

@llvm/pr-subscribers-backend-risc-v

Author: Sam Elliott (lenary)

Changes

---

Full diff: https://github.com/llvm/llvm-project/pull/201699.diff

2 Files Affected:

• (modified) compiler-rt/lib/builtins/cpu_model/riscv.c (+3)
• (modified) llvm/lib/Target/RISCV/RISCVFeatures.td (+2-1)

diff --git a/compiler-rt/lib/builtins/cpu_model/riscv.c b/compiler-rt/lib/builtins/cpu_model/riscv.c
index 1c729c8bd7e05..4a4e2176eb5fe 100644
--- a/compiler-rt/lib/builtins/cpu_model/riscv.c
+++ b/compiler-rt/lib/builtins/cpu_model/riscv.c
@@ -146,6 +146,9 @@ struct {
 #define ZIFENCEI_BITMASK (1ULL << 11)
 #define ZMMUL_GROUPID 1
 #define ZMMUL_BITMASK (1ULL << 12)
+// NOTE: Bits 13-26 are reserved per RISC-V C API doc PR #185.
+#define ZICFISS_GROUPID 1
+#define ZICFISS_BITMASK (1ULL << 27)
 
 #if defined(__linux__)
 
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 4da4cd2ebe303..a01c9b86ac2d5 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -181,7 +181,8 @@ def FeatureStdExtZicfilp
 
 def FeatureStdExtZicfiss
     : RISCVExperimentalExtension<1, 0, "Shadow stack",
-                                 [FeatureStdExtZicsr, FeatureStdExtZimop]>;
+                                 [FeatureStdExtZicsr, FeatureStdExtZimop]>,
+      RISCVExtensionBitmask<1, 27>;
 def HasStdExtZicfiss : Predicate<"Subtarget->hasStdExtZicfiss()">,
                        AssemblerPredicate<(all_of FeatureStdExtZicfiss),
                                           "'Zicfiss' (Shadow stack)">;

[topperc]

Should this be connect to hwprobe?

[lenary]

Should this be connect to hwprobe?

I didn't find a hwprobe in the risc-v linux docs, maybe it's just not documented?

[lenary]

It is indeed not documented :/ - https://github.com/torvalds/linux/blob/master/arch/riscv/include/uapi/asm/hwprobe.h

[github-actions]

✅ With the latest revision this PR passed the C/C++ code formatter.

[wangpc-pp]

I don't know which style is better.

We can fix the KEYVAR to EXTValue and change the value of EXTValue to different entries.

#define SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(EXTNAME) \
  SET_SINGLE_RISCV_FEATURE(EXTValue &RISCV_HWPROBE_EXT_##EXTNAME, EXTNAME)
// ...
unsigned long long EXTValue = Hwprobes[1].value;
// Query extensions in EXT0.
// ...
EXTValue = Hwprobes[5].value;
// Query extensions in EXT1.

[lenary]

If I did this, I'd probably want separate scopes for each EXTValue, rather than updating, so that we don't add an extension to the wrong block or confuse something else.

[wangpc-pp]

Using scoped braces is also an option. :-)
Anyway this is just a debatable suggestion, not blocking.

[wangpc-pp]

LGTM.