[AArch64] Enable software pipelining for the Cortex-A320 - #206072
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[AArch64] Enable software pipelining for the Cortex-A320#206072saturn691 wants to merge 2 commits into
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Software pipelining gives mostly positive performance improvements for the Cortex-A320. This enables MachinePipeliner for default for the Cortex-A320 and keeps the behaviour of -aarch64-enable-pipeliner for other CPUs.
MachinePipeliner has a cap of II=27 which is reasonable, but it rejects a subset of profitable loops. These are vectorised loops, that have not been interleaved by the Loop Vectorizer (i.e. loops written with intrinsics). However, this is still a draft, as we need to uncap the II limit in code. Also this is codex code, so there may be a better way to do this. Assisted-by: codex, reviewed and tested by me
🐧 Linux x64 Test Results
Failed Tests(click on a test name to see its output) LLVMLLVM.CodeGen/AArch64/O3-pipeline.llLLVM.CodeGen/AArch64/aarch64-swp-ws-live-intervals-1.mirLLVM.CodeGen/AArch64/aarch64-swp-ws-live-intervals.mirIf these failures are unrelated to your changes (for example tests are broken or flaky at HEAD), please open an issue at https://github.com/llvm/llvm-project/issues and add the |
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Software pipelining gives mostly positive performance improvements for the Cortex-A320. This enables MachinePipeliner for default for the Cortex-A320 and keeps the behaviour of -aarch64-enable-pipeliner for other CPUs.