[AMDGPU][GISel] Add RegBankLegalize rules for llvm.amdgcn.fdot2.bf16.bf16

[chinmaydd]

No description provided.

[llvmorg-github-actions]

@llvm/pr-subscribers-backend-amdgpu

Author: Chinmay Deshpande (chinmaydd)

Changes

---

Full diff: https://github.com/llvm/llvm-project/pull/214013.diff

2 Files Affected:

• (modified) llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp (+1-1)
• (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.bf16.bf16.ll (+76-3)

diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
index 881afaf920037..66a5e1bb378be 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
@@ -2619,7 +2619,7 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
       .Uni(S32, {{UniInVgprS32}, {IntrId, VgprV2S16, VgprV2S16, Vgpr32}})
       .Div(S32, {{Vgpr32}, {IntrId, VgprV2S16, VgprV2S16, Vgpr32}});
 
-  addRulesForIOpcs({amdgcn_fdot2_f16_f16}, Standard)
+  addRulesForIOpcs({amdgcn_fdot2_f16_f16, amdgcn_fdot2_bf16_bf16}, Standard)
       .Uni(S16, {{UniInVgprS16}, {IntrId, VgprV2S16, VgprV2S16, Vgpr16}})
       .Div(S16, {{Vgpr16}, {IntrId, VgprV2S16, VgprV2S16, Vgpr16}});
 
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.bf16.bf16.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.bf16.bf16.ll
index 82716f40524e6..e284f99fa05b6 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.bf16.bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.bf16.bf16.ll
@@ -1,9 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=amdgpu11.00 -mattr=+real-true16 < %s | FileCheck %s --check-prefixes=GFX11,SDAG-GFX11,SDAG-GFX11-TRUE16
 ; RUN: llc -mtriple=amdgpu11.00 -mattr=-real-true16 < %s | FileCheck %s --check-prefixes=GFX11,SDAG-GFX11,SDAG-GFX11-FAKE16
-; FIXME: GlobalIsel doesn't support BF16 for now.
-; xUN: llc -global-isel -mtriple=amdgpu11.00 -mattr=+real-true16 < %s | FileCheck %s --check-prefixes=GFX11,GISEL-GFX11,GISEL-GFX11-TRUE16
-; xUN: llc -global-isel -mtriple=amdgpu11.00 -mattr=-real-true16 < %s | FileCheck %s --check-prefixes=GFX11,GISEL-GFX11,GISEL-GFX11-FAKE16
+; RUN: llc -global-isel -mtriple=amdgpu11.00 -mattr=+real-true16 < %s | FileCheck %s --check-prefixes=GFX11,GISEL-GFX11,GISEL-GFX11-TRUE16
+; RUN: llc -global-isel -mtriple=amdgpu11.00 -mattr=-real-true16 < %s | FileCheck %s --check-prefixes=GFX11,GISEL-GFX11,GISEL-GFX11-FAKE16
 
 declare bfloat @llvm.amdgcn.fdot2.bf16.bf16(<2 x bfloat> %a, <2 x bfloat> %b, bfloat %c)
 
@@ -33,6 +32,36 @@ define amdgpu_kernel void @test_llvm_amdgcn_fdot2_bf16_bf16(
 ; SDAG-GFX11-FAKE16-NEXT:    v_dot2_bf16_bf16 v1, s2, s3, v1
 ; SDAG-GFX11-FAKE16-NEXT:    global_store_b16 v0, v1, s[0:1]
 ; SDAG-GFX11-FAKE16-NEXT:    s_endpgm
+;
+; GISEL-GFX11-TRUE16-LABEL: test_llvm_amdgcn_fdot2_bf16_bf16:
+; GISEL-GFX11-TRUE16:       ; %bb.0: ; %entry
+; GISEL-GFX11-TRUE16-NEXT:    s_load_b256 s[0:7], s[4:5], 0x24
+; GISEL-GFX11-TRUE16-NEXT:    v_mov_b32_e32 v1, 0
+; GISEL-GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GISEL-GFX11-TRUE16-NEXT:    s_load_b32 s2, s[2:3], 0x0
+; GISEL-GFX11-TRUE16-NEXT:    s_load_b32 s3, s[4:5], 0x0
+; GISEL-GFX11-TRUE16-NEXT:    global_load_d16_b16 v0, v1, s[6:7]
+; GISEL-GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GISEL-GFX11-TRUE16-NEXT:    v_dot2_bf16_bf16 v0.l, s2, s3, v0.l
+; GISEL-GFX11-TRUE16-NEXT:    global_store_b16 v1, v0, s[0:1]
+; GISEL-GFX11-TRUE16-NEXT:    s_endpgm
+;
+; GISEL-GFX11-FAKE16-LABEL: test_llvm_amdgcn_fdot2_bf16_bf16:
+; GISEL-GFX11-FAKE16:       ; %bb.0: ; %entry
+; GISEL-GFX11-FAKE16-NEXT:    s_load_b256 s[0:7], s[4:5], 0x24
+; GISEL-GFX11-FAKE16-NEXT:    v_mov_b32_e32 v0, 0
+; GISEL-GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GISEL-GFX11-FAKE16-NEXT:    s_load_b32 s2, s[2:3], 0x0
+; GISEL-GFX11-FAKE16-NEXT:    s_load_b32 s3, s[4:5], 0x0
+; GISEL-GFX11-FAKE16-NEXT:    global_load_u16 v1, v0, s[6:7]
+; GISEL-GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GISEL-GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s4, v1
+; GISEL-GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GISEL-GFX11-FAKE16-NEXT:    v_mov_b32_e32 v1, s4
+; GISEL-GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GISEL-GFX11-FAKE16-NEXT:    v_dot2_bf16_bf16 v1, s2, s3, v1
+; GISEL-GFX11-FAKE16-NEXT:    global_store_b16 v0, v1, s[0:1]
+; GISEL-GFX11-FAKE16-NEXT:    s_endpgm
     ptr addrspace(1) %r,
     ptr addrspace(1) %a,
     ptr addrspace(1) %b,
@@ -73,6 +102,33 @@ define amdgpu_kernel void @test_llvm_amdgcn_fdot2_bf16_bf16_dpp(
 ; SDAG-GFX11-FAKE16-NEXT:    v_dot2_bf16_bf16_e64_dpp v0, v2, v0, v1 quad_perm:[1,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; SDAG-GFX11-FAKE16-NEXT:    scratch_store_b16 off, v0, s0
 ; SDAG-GFX11-FAKE16-NEXT:    s_endpgm
+;
+; GISEL-GFX11-TRUE16-LABEL: test_llvm_amdgcn_fdot2_bf16_bf16_dpp:
+; GISEL-GFX11-TRUE16:       ; %bb.0: ; %entry
+; GISEL-GFX11-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GISEL-GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GISEL-GFX11-TRUE16-NEXT:    scratch_load_b32 v1, off, s1
+; GISEL-GFX11-TRUE16-NEXT:    scratch_load_b32 v2, off, s2
+; GISEL-GFX11-TRUE16-NEXT:    scratch_load_d16_b16 v0, off, s3
+; GISEL-GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(2)
+; GISEL-GFX11-TRUE16-NEXT:    v_mov_b32_dpp v1, v1 quad_perm:[1,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GISEL-GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GISEL-GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GISEL-GFX11-TRUE16-NEXT:    v_dot2_bf16_bf16 v0.l, v1, v2, v0.l
+; GISEL-GFX11-TRUE16-NEXT:    scratch_store_b16 off, v0, s0
+; GISEL-GFX11-TRUE16-NEXT:    s_endpgm
+;
+; GISEL-GFX11-FAKE16-LABEL: test_llvm_amdgcn_fdot2_bf16_bf16_dpp:
+; GISEL-GFX11-FAKE16:       ; %bb.0: ; %entry
+; GISEL-GFX11-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GISEL-GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GISEL-GFX11-FAKE16-NEXT:    scratch_load_b32 v0, off, s1
+; GISEL-GFX11-FAKE16-NEXT:    scratch_load_b32 v1, off, s2
+; GISEL-GFX11-FAKE16-NEXT:    scratch_load_u16 v2, off, s3
+; GISEL-GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GISEL-GFX11-FAKE16-NEXT:    v_dot2_bf16_bf16_e64_dpp v0, v0, v1, v2 quad_perm:[1,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GISEL-GFX11-FAKE16-NEXT:    scratch_store_b16 off, v0, s0
+; GISEL-GFX11-FAKE16-NEXT:    s_endpgm
     ptr addrspace(5) %r,
     ptr addrspace(5) %a,
     ptr addrspace(5) %b,
@@ -107,6 +163,22 @@ define amdgpu_ps void @test_llvm_amdgcn_fdot2_bf16_bf16_sis(
 ; SDAG-GFX11-FAKE16-NEXT:    v_dot2_bf16_bf16 v2, s0, 0x3f803f80, v2
 ; SDAG-GFX11-FAKE16-NEXT:    global_store_b16 v[0:1], v2, off
 ; SDAG-GFX11-FAKE16-NEXT:    s_endpgm
+;
+; GISEL-GFX11-TRUE16-LABEL: test_llvm_amdgcn_fdot2_bf16_bf16_sis:
+; GISEL-GFX11-TRUE16:       ; %bb.0: ; %entry
+; GISEL-GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, s1
+; GISEL-GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GISEL-GFX11-TRUE16-NEXT:    v_dot2_bf16_bf16 v2.l, s0, 0x3f803f80, v2.l
+; GISEL-GFX11-TRUE16-NEXT:    global_store_b16 v[0:1], v2, off
+; GISEL-GFX11-TRUE16-NEXT:    s_endpgm
+;
+; GISEL-GFX11-FAKE16-LABEL: test_llvm_amdgcn_fdot2_bf16_bf16_sis:
+; GISEL-GFX11-FAKE16:       ; %bb.0: ; %entry
+; GISEL-GFX11-FAKE16-NEXT:    v_mov_b32_e32 v2, s1
+; GISEL-GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GISEL-GFX11-FAKE16-NEXT:    v_dot2_bf16_bf16 v2, s0, 0x3f803f80, v2
+; GISEL-GFX11-FAKE16-NEXT:    global_store_b16 v[0:1], v2, off
+; GISEL-GFX11-FAKE16-NEXT:    s_endpgm
     ptr addrspace(1) %r,
     <2 x bfloat> inreg %a,
     bfloat inreg %c) {
@@ -119,4 +191,5 @@ entry:
 declare i32 @llvm.amdgcn.update.dpp.i32(i32, i32, i32, i32, i32, i1)
 ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
 ; GFX11: {{.*}}
+; GISEL-GFX11: {{.*}}
 ; SDAG-GFX11: {{.*}}