[AMDGPU] Autogen tests with new changes - #214286
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Change-Id: Id3635fa58a367495b11e98e6a2846f8994233d16
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@llvm/pr-subscribers-backend-amdgpu Author: Chinmay Deshpande (chinmaydd) ChangesFull diff: https://github.com/llvm/llvm-project/pull/214286.diff 2 Files Affected:
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.bf16.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.bf16.ll
index a6ab89b9b864b..640183a20e7ea 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.bf16.ll
@@ -33,7 +33,7 @@ define amdgpu_kernel void @rcp_bf16(ptr addrspace(1) %out, bfloat %src) #1 {
;
; GI-TRUE16-LABEL: rcp_bf16:
; GI-TRUE16: ; %bb.0:
-; GI-TRUE16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
+; GI-TRUE16-NEXT: global_prefetch_b8 v0, null scope:SCOPE_SE
; GI-TRUE16-NEXT: v_nop
; GI-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GI-TRUE16-NEXT: s_load_b96 s[0:2], s[4:5], 0x0 nv
@@ -45,7 +45,7 @@ define amdgpu_kernel void @rcp_bf16(ptr addrspace(1) %out, bfloat %src) #1 {
;
; GI-FAKE16-LABEL: rcp_bf16:
; GI-FAKE16: ; %bb.0:
-; GI-FAKE16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
+; GI-FAKE16-NEXT: global_prefetch_b8 v0, null scope:SCOPE_SE
; GI-FAKE16-NEXT: v_nop
; GI-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GI-FAKE16-NEXT: s_load_b96 s[0:2], s[4:5], 0x0 nv
@@ -62,7 +62,7 @@ define amdgpu_kernel void @rcp_bf16(ptr addrspace(1) %out, bfloat %src) #1 {
define amdgpu_kernel void @rcp_bf16_global_load(ptr addrspace(1) %out, ptr addrspace(1) %in) #1 {
; SDAG-TRUE16-LABEL: rcp_bf16_global_load:
; SDAG-TRUE16: ; %bb.0:
-; SDAG-TRUE16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
+; SDAG-TRUE16-NEXT: global_prefetch_b8 v0, null scope:SCOPE_SE
; SDAG-TRUE16-NEXT: v_nop
; SDAG-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; SDAG-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x0 nv
@@ -77,7 +77,7 @@ define amdgpu_kernel void @rcp_bf16_global_load(ptr addrspace(1) %out, ptr addrs
;
; SDAG-FAKE16-LABEL: rcp_bf16_global_load:
; SDAG-FAKE16: ; %bb.0:
-; SDAG-FAKE16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
+; SDAG-FAKE16-NEXT: global_prefetch_b8 v0, null scope:SCOPE_SE
; SDAG-FAKE16-NEXT: v_nop
; SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; SDAG-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x0 nv
@@ -92,7 +92,7 @@ define amdgpu_kernel void @rcp_bf16_global_load(ptr addrspace(1) %out, ptr addrs
;
; GI-TRUE16-LABEL: rcp_bf16_global_load:
; GI-TRUE16: ; %bb.0:
-; GI-TRUE16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
+; GI-TRUE16-NEXT: global_prefetch_b8 v0, null scope:SCOPE_SE
; GI-TRUE16-NEXT: v_nop
; GI-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GI-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x0 nv
@@ -107,7 +107,7 @@ define amdgpu_kernel void @rcp_bf16_global_load(ptr addrspace(1) %out, ptr addrs
;
; GI-FAKE16-LABEL: rcp_bf16_global_load:
; GI-FAKE16: ; %bb.0:
-; GI-FAKE16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
+; GI-FAKE16-NEXT: global_prefetch_b8 v0, null scope:SCOPE_SE
; GI-FAKE16-NEXT: v_nop
; GI-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GI-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x0 nv
@@ -153,7 +153,7 @@ define amdgpu_kernel void @rcp_bf16_constant_4(ptr addrspace(1) %out) #1 {
;
; GI-TRUE16-LABEL: rcp_bf16_constant_4:
; GI-TRUE16: ; %bb.0:
-; GI-TRUE16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
+; GI-TRUE16-NEXT: global_prefetch_b8 v0, null scope:SCOPE_SE
; GI-TRUE16-NEXT: v_nop
; GI-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GI-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 nv
@@ -165,7 +165,7 @@ define amdgpu_kernel void @rcp_bf16_constant_4(ptr addrspace(1) %out) #1 {
;
; GI-FAKE16-LABEL: rcp_bf16_constant_4:
; GI-FAKE16: ; %bb.0:
-; GI-FAKE16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
+; GI-FAKE16-NEXT: global_prefetch_b8 v0, null scope:SCOPE_SE
; GI-FAKE16-NEXT: v_nop
; GI-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GI-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 nv
@@ -205,7 +205,7 @@ define amdgpu_kernel void @rcp_bf16_constant_100(ptr addrspace(1) %out) #1 {
;
; GI-TRUE16-LABEL: rcp_bf16_constant_100:
; GI-TRUE16: ; %bb.0:
-; GI-TRUE16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
+; GI-TRUE16-NEXT: global_prefetch_b8 v0, null scope:SCOPE_SE
; GI-TRUE16-NEXT: v_nop
; GI-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GI-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 nv
@@ -217,7 +217,7 @@ define amdgpu_kernel void @rcp_bf16_constant_100(ptr addrspace(1) %out) #1 {
;
; GI-FAKE16-LABEL: rcp_bf16_constant_100:
; GI-FAKE16: ; %bb.0:
-; GI-FAKE16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
+; GI-FAKE16-NEXT: global_prefetch_b8 v0, null scope:SCOPE_SE
; GI-FAKE16-NEXT: v_nop
; GI-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GI-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 nv
@@ -257,7 +257,7 @@ define amdgpu_kernel void @rcp_undef_bf16(ptr addrspace(1) %out) #1 {
;
; GI-TRUE16-LABEL: rcp_undef_bf16:
; GI-TRUE16: ; %bb.0:
-; GI-TRUE16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
+; GI-TRUE16-NEXT: global_prefetch_b8 v0, null scope:SCOPE_SE
; GI-TRUE16-NEXT: v_nop
; GI-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GI-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 nv
@@ -269,7 +269,7 @@ define amdgpu_kernel void @rcp_undef_bf16(ptr addrspace(1) %out) #1 {
;
; GI-FAKE16-LABEL: rcp_undef_bf16:
; GI-FAKE16: ; %bb.0:
-; GI-FAKE16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
+; GI-FAKE16-NEXT: global_prefetch_b8 v0, null scope:SCOPE_SE
; GI-FAKE16-NEXT: v_nop
; GI-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GI-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 nv
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.bf16.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.bf16.ll
index e6b76785aa116..859206cb07d7e 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.bf16.ll
@@ -33,7 +33,7 @@ define amdgpu_kernel void @rsq_bf16(ptr addrspace(1) %out, bfloat %src) #1 {
;
; GISEL-REAL16-LABEL: rsq_bf16:
; GISEL-REAL16: ; %bb.0:
-; GISEL-REAL16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
+; GISEL-REAL16-NEXT: global_prefetch_b8 v0, null scope:SCOPE_SE
; GISEL-REAL16-NEXT: v_nop
; GISEL-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GISEL-REAL16-NEXT: s_load_b96 s[0:2], s[4:5], 0x0 nv
@@ -45,7 +45,7 @@ define amdgpu_kernel void @rsq_bf16(ptr addrspace(1) %out, bfloat %src) #1 {
;
; GISEL-FAKE16-LABEL: rsq_bf16:
; GISEL-FAKE16: ; %bb.0:
-; GISEL-FAKE16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
+; GISEL-FAKE16-NEXT: global_prefetch_b8 v0, null scope:SCOPE_SE
; GISEL-FAKE16-NEXT: v_nop
; GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GISEL-FAKE16-NEXT: s_load_b96 s[0:2], s[4:5], 0x0 nv
@@ -86,7 +86,7 @@ define amdgpu_kernel void @rsq_bf16_constant_4(ptr addrspace(1) %out) #1 {
;
; GISEL-REAL16-LABEL: rsq_bf16_constant_4:
; GISEL-REAL16: ; %bb.0:
-; GISEL-REAL16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
+; GISEL-REAL16-NEXT: global_prefetch_b8 v0, null scope:SCOPE_SE
; GISEL-REAL16-NEXT: v_nop
; GISEL-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GISEL-REAL16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 nv
@@ -98,7 +98,7 @@ define amdgpu_kernel void @rsq_bf16_constant_4(ptr addrspace(1) %out) #1 {
;
; GISEL-FAKE16-LABEL: rsq_bf16_constant_4:
; GISEL-FAKE16: ; %bb.0:
-; GISEL-FAKE16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
+; GISEL-FAKE16-NEXT: global_prefetch_b8 v0, null scope:SCOPE_SE
; GISEL-FAKE16-NEXT: v_nop
; GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GISEL-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 nv
@@ -139,7 +139,7 @@ define amdgpu_kernel void @rsq_bf16_constant_100(ptr addrspace(1) %out) #1 {
;
; GISEL-REAL16-LABEL: rsq_bf16_constant_100:
; GISEL-REAL16: ; %bb.0:
-; GISEL-REAL16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
+; GISEL-REAL16-NEXT: global_prefetch_b8 v0, null scope:SCOPE_SE
; GISEL-REAL16-NEXT: v_nop
; GISEL-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GISEL-REAL16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 nv
@@ -151,7 +151,7 @@ define amdgpu_kernel void @rsq_bf16_constant_100(ptr addrspace(1) %out) #1 {
;
; GISEL-FAKE16-LABEL: rsq_bf16_constant_100:
; GISEL-FAKE16: ; %bb.0:
-; GISEL-FAKE16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
+; GISEL-FAKE16-NEXT: global_prefetch_b8 v0, null scope:SCOPE_SE
; GISEL-FAKE16-NEXT: v_nop
; GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GISEL-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 nv
@@ -182,7 +182,7 @@ define amdgpu_kernel void @rsq_undef_bf16(ptr addrspace(1) %out) #1 {
;
; GISEL-REAL16-LABEL: rsq_undef_bf16:
; GISEL-REAL16: ; %bb.0:
-; GISEL-REAL16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
+; GISEL-REAL16-NEXT: global_prefetch_b8 v0, null scope:SCOPE_SE
; GISEL-REAL16-NEXT: v_nop
; GISEL-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GISEL-REAL16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 nv
@@ -194,7 +194,7 @@ define amdgpu_kernel void @rsq_undef_bf16(ptr addrspace(1) %out) #1 {
;
; GISEL-FAKE16-LABEL: rsq_undef_bf16:
; GISEL-FAKE16: ; %bb.0:
-; GISEL-FAKE16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
+; GISEL-FAKE16-NEXT: global_prefetch_b8 v0, null scope:SCOPE_SE
; GISEL-FAKE16-NEXT: v_nop
; GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GISEL-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 nv
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chinmaydd
enabled auto-merge (squash)
August 5, 2026 17:07
shiltian
approved these changes
Aug 5, 2026
shiltian
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shiltian
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There was a problem hiding this comment.
Yeah, the merge order is really a thing.
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Missed in #214040