[RISCV] Remove VeryonV1 processor definition - #220623
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@llvm/pr-subscribers-clang-driver @llvm/pr-subscribers-backend-risc-v Author: Ryan Buchner (bababuck) ChangesThis processor isn't used by anyone and removing it will pave the way for removal on the Full diff: https://github.com/llvm/llvm-project/pull/220623.diff 7 Files Affected:
diff --git a/clang/test/CodeGen/RISCV/builtin-cpu-is.c b/clang/test/CodeGen/RISCV/builtin-cpu-is.c
index 74b7e2e49eb21..d87af8fb5d7f5 100644
--- a/clang/test/CodeGen/RISCV/builtin-cpu-is.c
+++ b/clang/test/CodeGen/RISCV/builtin-cpu-is.c
@@ -2,26 +2,8 @@
// RUN: %clang_cc1 -triple riscv64-unknown-linux-gnu -disable-O0-optnone -emit-llvm %s -o - \
// RUN: | opt -S -passes=mem2reg | FileCheck %s --check-prefix=CHECK-RV64
-// CHECK-RV64-LABEL: define dso_local signext i32 @test_cpu_is_veyron_v1(
-// CHECK-RV64-SAME: ) #[[ATTR0:[0-9]+]] {
-// CHECK-RV64-NEXT: [[ENTRY:.*:]]
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = load i32, ptr @__riscv_cpu_model, align 4
-// CHECK-RV64-NEXT: [[TMP1:%.*]] = icmp eq i32 [[TMP0]], 1567
-// CHECK-RV64-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr inbounds nuw (i8, ptr @__riscv_cpu_model, i64 8), align 8
-// CHECK-RV64-NEXT: [[TMP3:%.*]] = icmp eq i64 [[TMP2]], -9223372036854710272
-// CHECK-RV64-NEXT: [[TMP4:%.*]] = and i1 [[TMP1]], [[TMP3]]
-// CHECK-RV64-NEXT: [[TMP5:%.*]] = load i64, ptr getelementptr inbounds nuw (i8, ptr @__riscv_cpu_model, i64 16), align 8
-// CHECK-RV64-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 273
-// CHECK-RV64-NEXT: [[TMP7:%.*]] = and i1 [[TMP4]], [[TMP6]]
-// CHECK-RV64-NEXT: [[CONV:%.*]] = zext i1 [[TMP7]] to i32
-// CHECK-RV64-NEXT: ret i32 [[CONV]]
-//
-int test_cpu_is_veyron_v1() {
- return __builtin_cpu_is("veyron-v1");
-}
-
// CHECK-RV64-LABEL: define dso_local signext i32 @test_cpu_is_spacemit_x60(
-// CHECK-RV64-SAME: ) #[[ATTR0]] {
+// CHECK-RV64-SAME: ) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: [[ENTRY:.*:]]
// CHECK-RV64-NEXT: [[TMP0:%.*]] = load i32, ptr @__riscv_cpu_model, align 4
// CHECK-RV64-NEXT: [[TMP1:%.*]] = icmp eq i32 [[TMP0]], 1808
diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index 89a3875adeed8..50d7ab7ab51b9 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -250,31 +250,6 @@
// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+svpbmt"
// MCPU-TT-ASCALON-X-SAME: "-target-abi" "lp64d"
-// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=veyron-v1 | FileCheck -check-prefix=MCPU-VEYRON-V1 %s
-// MCPU-VEYRON-V1: "-target-cpu" "veyron-v1"
-// MCPU-VEYRON-V1: "-target-feature" "+m"
-// MCPU-VEYRON-V1: "-target-feature" "+a"
-// MCPU-VEYRON-V1: "-target-feature" "+f"
-// MCPU-VEYRON-V1: "-target-feature" "+d"
-// MCPU-VEYRON-V1: "-target-feature" "+c"
-// MCPU-VEYRON-V1: "-target-feature" "+zicbom"
-// MCPU-VEYRON-V1: "-target-feature" "+zicbop"
-// MCPU-VEYRON-V1: "-target-feature" "+zicboz"
-// MCPU-VEYRON-V1: "-target-feature" "+zicntr"
-// MCPU-VEYRON-V1: "-target-feature" "+zicsr"
-// MCPU-VEYRON-V1: "-target-feature" "+zifencei"
-// MCPU-VEYRON-V1: "-target-feature" "+zihintpause"
-// MCPU-VEYRON-V1: "-target-feature" "+zihpm"
-// MCPU-VEYRON-V1: "-target-feature" "+zba"
-// MCPU-VEYRON-V1: "-target-feature" "+zbb"
-// MCPU-VEYRON-V1: "-target-feature" "+zbc"
-// MCPU-VEYRON-V1: "-target-feature" "+zbs"
-// MCPU-VEYRON-V1: "-target-feature" "+xventanacondops"
-// MCPU-VEYRON-V1: "-target-abi" "lp64d"
-
-// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=veyron-v1 | FileCheck -check-prefix=MTUNE-VEYRON-V1 %s
-// MTUNE-VEYRON-V1: "-tune-cpu" "veyron-v1"
-
// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=xiangshan-nanhu | FileCheck -check-prefix=MTUNE-XIANGSHAN-NANHU %s
// MTUNE-XIANGSHAN-NANHU: "-tune-cpu" "xiangshan-nanhu"
diff --git a/clang/test/Misc/target-invalid-cpu-note/riscv.c b/clang/test/Misc/target-invalid-cpu-note/riscv.c
index 234cc82a2bab6..546dbbdb7e043 100644
--- a/clang/test/Misc/target-invalid-cpu-note/riscv.c
+++ b/clang/test/Misc/target-invalid-cpu-note/riscv.c
@@ -59,7 +59,6 @@
// RISCV64-SAME: {{^}}, syntacore-scr5-rv64
// RISCV64-SAME: {{^}}, syntacore-scr7
// RISCV64-SAME: {{^}}, tt-ascalon-x
-// RISCV64-SAME: {{^}}, veyron-v1
// RISCV64-SAME: {{^}}, xiangshan-kunminghu
// RISCV64-SAME: {{^}}, xiangshan-nanhu
// RISCV64-SAME: {{^}}, xt-c910v2
@@ -128,7 +127,6 @@
// TUNE-RISCV64-SAME: {{^}}, syntacore-scr5-rv64
// TUNE-RISCV64-SAME: {{^}}, syntacore-scr7
// TUNE-RISCV64-SAME: {{^}}, tt-ascalon-x
-// TUNE-RISCV64-SAME: {{^}}, veyron-v1
// TUNE-RISCV64-SAME: {{^}}, xiangshan-kunminghu
// TUNE-RISCV64-SAME: {{^}}, xiangshan-nanhu
// TUNE-RISCV64-SAME: {{^}}, xt-c910v2
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index d388e0ea81c19..9890551eda341 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -2238,7 +2238,3 @@ def TuneMIPSP8700
def TuneSiFive7 : SubtargetFeature<"sifive7", "RISCVProcFamily", "SiFive7",
"SiFive 7-Series processors", [], InlineIgnore>;
-
-def TuneVentanaVeyron : SubtargetFeature<"ventana-veyron", "RISCVProcFamily", "VentanaVeyron",
- "Ventana Veyron-Series processors",
- [], InlineIgnore>;
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td
index b1f7f99d63f66..7fe808e254b7f 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -764,45 +764,6 @@ def TENSTORRENT_ASCALON_X : RISCVProcessorModel<"tt-ascalon-x",
TuneOptimizedZeroStrideLoad,
TunePostRAScheduler]>;
-def VENTANA_VEYRON_V1 : RISCVProcessorModel<"veyron-v1",
- NoSchedModel,
- [Feature64Bit,
- FeatureStdExtI,
- FeatureStdExtZifencei,
- FeatureStdExtZicsr,
- FeatureStdExtZicntr,
- FeatureStdExtZihpm,
- FeatureStdExtZihintpause,
- FeatureStdExtM,
- FeatureStdExtA,
- FeatureStdExtF,
- FeatureStdExtD,
- FeatureStdExtC,
- FeatureStdExtZba,
- FeatureStdExtZbb,
- FeatureStdExtZbc,
- FeatureStdExtZbs,
- FeatureStdExtZicbom,
- FeatureStdExtZicbop,
- FeatureStdExtZicboz,
- FeatureVendorXVentanaCondOps],
- [TuneVentanaVeyron,
- TuneDisableMISchedLoadClustering,
- TuneDisablePostMISchedLoadClustering,
- TuneDisablePostMISchedStoreClustering,
- TuneLUIADDIFusion,
- TuneAUIPCADDIFusion,
- TuneZExtHFusion,
- TuneZExtWFusion,
- TuneShiftedZExtWFusion,
- TuneADDLoadFusion,
- TuneAUIPCLoadFusion,
- TuneLUILoadFusion]> {
- let MVendorID = 0x61f;
- let MArchID = 0x8000000000010000;
- let MImpID = 0x111;
-}
-
def XIANGSHAN_NANHU : RISCVProcessorModel<"xiangshan-nanhu",
XiangShanNanHuModel,
[Feature64Bit,
diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h
index 14c33ee8691ec..3add69d4bf9b8 100644
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -87,7 +87,6 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
enum RISCVProcFamilyEnum : uint8_t {
Others,
SiFive7,
- VentanaVeyron,
MIPSP8700,
Andes45,
};
diff --git a/llvm/test/CodeGen/RISCV/features-info.ll b/llvm/test/CodeGen/RISCV/features-info.ll
index b756a2f862b7d..ab2ae3da0e99f 100644
--- a/llvm/test/CodeGen/RISCV/features-info.ll
+++ b/llvm/test/CodeGen/RISCV/features-info.ll
@@ -211,7 +211,6 @@
; CHECK-NEXT: unaligned-vector-mem - Has reasonably performant unaligned vector loads and stores.
; CHECK-NEXT: use-postra-scheduler - Schedule again after register allocation.
; CHECK-NEXT: v - 'V' (Vector Extension for Application Processors).
-; CHECK-NEXT: ventana-veyron - Ventana Veyron-Series processors.
; CHECK-NEXT: vl-dependent-latency - Latency of vector instructions is dependent on the dynamic value of vl.
; CHECK-NEXT: vxrm-pipeline-flush - VXRM writes causes pipeline flush.
; CHECK-NEXT: xaifet - 'XAIFET' (AI Foundry ET Extension).
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| @@ -217,14 +217,12 @@ Makes programs 10x faster by doing Special New Thing. | |||
| push/pop extensions. | |||
| * Bump Svukte extension to 1.0. | |||
| * Remove experimental from Zicfiss. | |||
| * Added support for `Sspmp`, `Sspmpen` and `Smpmpdeleg` extensions. | |||
| * Removes veyron-v1 processor definition and tuning model. | |||
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Nit (on the release notes in general): Looks like there isn't a set "tense" used on verbs in the release notes.
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This processor isn't used by anyone and removing it will pave the way for removal on the
VentanaCondOps.