v1.0.0

bust 1.0.0

bust 1.0 is a rewrite of bust 0.14. It generates the register file of a register map from a JSON file for FPGA or ASIC modules. From one file it writes the VHDL register file with its bus endpoint, a self-checking UVVM testbench, C, C++ and Python headers, and documentation.

Install it with pip install bust. It needs Python 3.9 or newer.

Features

• Six buses: AXI4-Lite, IPBus, SBI (the UVVM simple bus interface), Avalon-MM, Wishbone and APB.
• Your design reaches every field by name through the to_hw and from_hw VHDL records, and enumerated fields become VHDL enumeration types.
• Separate software and hardware access per field, with SystemRDL-style side effects: clear or set on read, set, clear or toggle on write, single-cycle pulses, hardware set and clear, write enables and access strobes.
• A self-checking UVVM testbench for every module, on every bus.
• The base address is a VHDL generic, so one module can sit at any or even multiple addresses.
• C, C++ and Python headers, an IPBus address table for uHAL and documentation from the same file.
• Every output carries the module version and a hash of the register map, and the hash and version register types let software check which register map the hardware holds.
• bust checks the register map and lists every problem in one run, with the file, line and path.
• Register maps can be written in JSON5, with comments and trailing commas.
• A new full-screen editor behind bust -c and bust -e.

The documentation is at bust.readthedocs.io. Report bugs and ideas as GitHub issues.