[rtl] Implement cycle/instret/time/hmpcountern CSRs

[GregAC]

The cycle/instret/time/hmpcountern CSRs are optionally accessible from U-mode. In Ibex we hardwire mcounteren to 0 meaning these counters cannot be accessed from U-mode. However they are still accessible from M-mode. Ibex currently doesn't implement them at all which isn't standards compliant. They should be implemented.

[GregAC]

Additional reads of these should be stimulated in DV and coverage added

[GregAC]

I have asked the riscv-privileged list if my understanding here is correct but it looks pretty clear from the spec and the fact the compliance tests specifically test accessing these CSRs from M mode.

[GregAC]

After some further digging there's an argument you don't need to implement these going by the latest spec draft, if you don't implement Zicntr (which we don't currently). I'm going to push this out of M2.5 due to this ambiguity. Solution here is likely to implement Zicntr.