Observed Behavior
When running the RTL simulation build for core_ibex with VCS, the build fails at the "Building RTL testbench" stage. The simulation is launched from ~/ibex/dv/uvm/core_ibex using the following command:
make TEST=riscv_arithmetic_basic_test SIMULATOR=vcs COSIM=1 ISS=spike COV=1
The console output is:
Building RTL testbench
make[1]: *** [scripts/ibex_sim.mk:42: out/metadata/tb.compile.stamp] Error 255
make: *** [Makefile:72: run] Error 2
VCS reports the following error:
Error-[XMRE] Cross-module reference resolution error
~/ibex/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv, 193
Error found while trying to resolve cross-module reference.
token 'gen_rdata_mux_check'. Originating module 'core_ibex_tb_top', first
module hit 'core_ibex_tb_top'.
Source info: $asserton(0,
core_ibex_tb_top.dut.u_ibex_top.gen_regfile_ff.register_file_i.gen_rdata_mux_check.u_rdata_a_mux.SelIsOnehot_A);
A similar error occurs at line 195:
Error-[XMRE] Cross-module reference resolution error
~/ibex/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv, 195
Error found while trying to resolve cross-module reference.
token 'gen_rdata_mux_check'.
Source info: $asserton(0,
core_ibex_tb_top.dut.u_ibex_top.gen_regfile_ff.register_file_i.gen_rdata_mux_check.u_rdata_b_mux.SelIsOnehot_A);
The issue consistently reproduces on all commits after 19592a1fc7ba7e85427906cd4d86b8356b91a45d (last known working commit) up to the current commit 31bf434d9000f02e29d3487e942b123c6e377a3a.
Attached the launch log compile_tb.log
Expected Behavior
The RTL testbench should compile successfully, and the simulation should proceed to execution of Generating core configuration file without cross-module reference resolution errors.
Steps to Reproduce the Issue
-
Checkout any commit after 19592a1fc7ba7e85427906cd4d86b8356b91a45d.
-
Navigate to ~/ibex/dv/uvm/core_ibex.
-
Run:
make TEST=riscv_arithmetic_basic_test SIMULATOR=vcs COSIM=1 ISS=spike COV=1
The compilation fails during the "Building RTL testbench" stage. No local modifications were made to the Ibex source code.
My Environment
EDA tool and version: Synopsys VCS S-2021.09
(vcs script version: S-2021.09, machine OS: Linux 5.15.0-164-generic)
Operating system: Rocky Linux release 8.10
Version of the Ibex source code:
Last working commit: 19592a1fc7ba7e85427906cd4d86b8356b91a45d
Failing commits: all subsequent commits up to 31bf434d9000f02e29d3487e942b123c6e377a3a
No local changes were made to the source code.
Observed Behavior
When running the RTL simulation build for
core_ibexwith VCS, the build fails at the "Building RTL testbench" stage. The simulation is launched from~/ibex/dv/uvm/core_ibexusing the following command:The console output is:
VCS reports the following error:
A similar error occurs at line 195:
The issue consistently reproduces on all commits after
19592a1fc7ba7e85427906cd4d86b8356b91a45d(last known working commit) up to the current commit31bf434d9000f02e29d3487e942b123c6e377a3a.Attached the launch log compile_tb.log
Expected Behavior
The RTL testbench should compile successfully, and the simulation should proceed to execution of
Generating core configuration filewithout cross-module reference resolution errors.Steps to Reproduce the Issue
Checkout any commit after
19592a1fc7ba7e85427906cd4d86b8356b91a45d.Navigate to
~/ibex/dv/uvm/core_ibex.Run:
The compilation fails during the "Building RTL testbench" stage. No local modifications were made to the Ibex source code.
My Environment
EDA tool and version: Synopsys VCS S-2021.09
(vcs script version: S-2021.09, machine OS: Linux 5.15.0-164-generic)
Operating system: Rocky Linux release 8.10
Version of the Ibex source code:
Last working commit:
19592a1fc7ba7e85427906cd4d86b8356b91a45dFailing commits: all subsequent commits up to
31bf434d9000f02e29d3487e942b123c6e377a3aNo local changes were made to the source code.