[secded] Switch to inverted ECC codes #1482
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Update code from upstream repository https://github.com/lowRISC/opentitan to revision 34ba5e45f9af7d8ca6c9bdae8bd11eeeeb669d6c * [dv] Add new ECC code options to mem_bkdr_util (Michael Schaffner) * [secded_gen] Define and generate inverted ECC enc/dec modules (Michael Schaffner) * [dv] Only run registers through one csr_rw sequence at once (Rupert Swarbrick) * [alert_handler] Minor lint fix (Michael Schaffner) * [prim_clock_div] Fix minor Verilator lint warning (Michael Schaffner) * [dvsim/lint] Make message reporting more flexible (Michael Schaffner) * [lint] Unify lint parser scripts (Michael Schaffner) * [rom_cntrl, dv] Test to verify successful rom check (Prajwala Puttappa) * [dv, dv_macros] Enhance `DV_GET_ENUM_PLUSARG` macro (Srikrishna Iyer) * [sram/dv] Fix mem data check (Weicai Yang) * [prim] Add flop wrapper for sparse fsm (Timothy Chen) * [flash_ctrl] Make data / metadata memories a single entry (Timothy Chen) * [dv] Teach encrypt/decrypt_sram_data to support OTBN (Rupert Swarbrick) Signed-off-by: Michael Schaffner <msf@google.com>
Signed-off-by: Michael Schaffner <msf@google.com>
tjaychen
reviewed
Dec 2, 2021
| csr_base_seq m_csr_seq; | ||
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| // env needs to have a ral instance | ||
| virtual task run_csr_vseq(string csr_test_type = "", |
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No they are not really. I.e., the first commit just vendors the newest prims over into Ibex - and that includes some dv functions.
tjaychen
approved these changes
Dec 2, 2021
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This vendors the inverted ECC codes into Ibex and switches over to them.