Skip to content

[dv, fcov] Increase iterations of riscv_mem_intg_error_test #2051

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 1 commit into from
Jun 22, 2023
Merged

[dv, fcov] Increase iterations of riscv_mem_intg_error_test #2051

Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
2 changes: 1 addition & 1 deletion dv/uvm/core_ibex/riscv_dv_extension/testlist.yaml
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -606,7 +606,7 @@
- test: riscv_mem_intg_error_test
description: >
Normal random instruction test, but randomly insert memory load/store integrity errors
iterations: 15
iterations: 50
gen_test: riscv_rand_instr_test
gen_opts: >
+require_signature_addr=1
Expand Down