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Merged
vogelpi merged 1 commit into from
Apr 9, 2026
Merged

[icache/rtl] Tweak infection #2376

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45 changes: 23 additions & 22 deletions doc/02_user/integration.rst
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Original file line number Diff line number Diff line change
Expand Up @@ -89,28 +89,29 @@ Instantiation Template
.. code-block:: verilog

ibex_top #(
.PMPEnable ( 0 ),
.PMPGranularity ( 0 ),
.PMPNumRegions ( 4 ),
.MHPMCounterNum ( 0 ),
.MHPMCounterWidth ( 40 ),
.RV32E ( 0 ),
.RV32M ( ibex_pkg::RV32MFast ),
.RV32B ( ibex_pkg::RV32BNone ),
.RV32ZC ( ibex_pkg::RV32ZcaZcbZcmp ),
.RegFile ( ibex_pkg::RegFileFF ),
.ICache ( 0 ),
.ICacheECC ( 0 ),
.ICacheScramble ( 0 ),
.BranchPrediction ( 0 ),
.SecureIbex ( 0 ),
.RndCnstLfsrSeed ( ibex_pkg::RndCnstLfsrSeedDefault ),
.RndCnstLfsrPerm ( ibex_pkg::RndCnstLfsrPermDefault ),
.DbgTriggerEn ( 0 ),
.DmBaseAddr ( 32'h1A110000 ),
.DmAddrMask ( 32'h00000FFF ),
.DmHaltAddr ( 32'h1A110800 ),
.DmExceptionAddr ( 32'h1A110808 )
.PMPEnable ( 0 ),
.PMPGranularity ( 0 ),
.PMPNumRegions ( 4 ),
.MHPMCounterNum ( 0 ),
.MHPMCounterWidth ( 40 ),
.RV32E ( 0 ),
.RV32M ( ibex_pkg::RV32MFast ),
.RV32B ( ibex_pkg::RV32BNone ),
.RV32ZC ( ibex_pkg::RV32ZcaZcbZcmp ),
.RegFile ( ibex_pkg::RegFileFF ),
.ICache ( 0 ),
.ICacheECC ( 0 ),
.ICacheTweakInfection ( 0 ),
.ICacheScramble ( 0 ),
.BranchPrediction ( 0 ),
.SecureIbex ( 0 ),
.RndCnstLfsrSeed ( ibex_pkg::RndCnstLfsrSeedDefault ),
.RndCnstLfsrPerm ( ibex_pkg::RndCnstLfsrPermDefault ),
.DbgTriggerEn ( 0 ),
.DmBaseAddr ( 32'h1A110000 ),
.DmAddrMask ( 32'h00000FFF ),
.DmHaltAddr ( 32'h1A110800 ),
.DmExceptionAddr ( 32'h1A110808 )
) u_top (
// Clock and reset
.clk_i (),
Expand Down
48 changes: 25 additions & 23 deletions dv/riscv_compliance/rtl/ibex_riscv_compliance.sv
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Expand Up @@ -29,6 +29,7 @@ module ibex_riscv_compliance (
parameter bit WritebackStage = 1'b0;
parameter bit ICache = 1'b0;
parameter bit ICacheECC = 1'b0;
parameter bit ICacheTweakInfection = 1'b0;
parameter bit BranchPredictor = 1'b0;
parameter bit SecureIbex = 1'b0;
parameter int unsigned LockstepOffset = 1;
Expand Down Expand Up @@ -140,29 +141,30 @@ module ibex_riscv_compliance (
end

ibex_top_tracing #(
.PMPEnable (PMPEnable ),
.PMPGranularity (PMPGranularity ),
.PMPNumRegions (PMPNumRegions ),
.MHPMCounterNum (MHPMCounterNum ),
.MHPMCounterWidth (MHPMCounterWidth ),
.RV32E (RV32E ),
.RV32M (RV32M ),
.RV32B (RV32B ),
.RV32ZC (RV32ZC ),
.RegFile (RegFile ),
.BranchTargetALU (BranchTargetALU ),
.WritebackStage (WritebackStage ),
.ICache (ICache ),
.ICacheECC (ICacheECC ),
.BranchPredictor (BranchPredictor ),
.DbgTriggerEn (DbgTriggerEn ),
.SecureIbex (SecureIbex ),
.LockstepOffset (LockstepOffset ),
.ICacheScramble (ICacheScramble ),
.DmBaseAddr (32'h00000000 ),
.DmAddrMask (32'h00000003 ),
.DmHaltAddr (32'h00000000 ),
.DmExceptionAddr (32'h00000000 )
.PMPEnable (PMPEnable ),
.PMPGranularity (PMPGranularity ),
.PMPNumRegions (PMPNumRegions ),
.MHPMCounterNum (MHPMCounterNum ),
.MHPMCounterWidth (MHPMCounterWidth ),
.RV32E (RV32E ),
.RV32M (RV32M ),
.RV32B (RV32B ),
.RV32ZC (RV32ZC ),
.RegFile (RegFile ),
.BranchTargetALU (BranchTargetALU ),
.WritebackStage (WritebackStage ),
.ICache (ICache ),
.ICacheECC (ICacheECC ),
.ICacheTweakInfection (ICacheTweakInfection),
.BranchPredictor (BranchPredictor ),
.DbgTriggerEn (DbgTriggerEn ),
.SecureIbex (SecureIbex ),
.LockstepOffset (LockstepOffset ),
.ICacheScramble (ICacheScramble ),
.DmBaseAddr (32'h00000000 ),
.DmAddrMask (32'h00000003 ),
.DmHaltAddr (32'h00000000 ),
.DmExceptionAddr (32'h00000000 )
) u_top (
.clk_i (clk_sys ),
.rst_ni (rst_sys_n ),
Expand Down
46 changes: 24 additions & 22 deletions dv/uvm/core_ibex/tb/core_ibex_tb_top.sv
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Expand Up @@ -66,6 +66,7 @@ module core_ibex_tb_top;
parameter bit WritebackStage = 1'b0;
parameter bit ICache = 1'b0;
parameter bit ICacheECC = 1'b0;
parameter bit ICacheTweakInfection = 1'b0;
parameter bit BranchPredictor = 1'b0;
parameter bit SecureIbex = 1'b0;
parameter int unsigned LockstepOffset = 1;
Expand Down Expand Up @@ -94,28 +95,29 @@ module core_ibex_tb_top;
assign {scramble_key, scramble_nonce} = scrambling_key_if.d_data;

ibex_top_tracing #(
.PMPEnable (PMPEnable ),
.PMPGranularity (PMPGranularity ),
.PMPNumRegions (PMPNumRegions ),
.MHPMCounterNum (MHPMCounterNum ),
.MHPMCounterWidth (MHPMCounterWidth ),
.RV32E (RV32E ),
.RV32M (RV32M ),
.RV32B (RV32B ),
.RegFile (RegFile ),
.BranchTargetALU (BranchTargetALU ),
.WritebackStage (WritebackStage ),
.ICache (ICache ),
.ICacheECC (ICacheECC ),
.SecureIbex (SecureIbex ),
.LockstepOffset (LockstepOffset ),
.ICacheScramble (ICacheScramble ),
.BranchPredictor (BranchPredictor ),
.DbgTriggerEn (DbgTriggerEn ),
.DmBaseAddr (DmBaseAddr ),
.DmAddrMask (DmAddrMask ),
.DmHaltAddr (DmHaltAddr ),
.DmExceptionAddr (DmExceptionAddr )
.PMPEnable (PMPEnable ),
.PMPGranularity (PMPGranularity ),
.PMPNumRegions (PMPNumRegions ),
.MHPMCounterNum (MHPMCounterNum ),
.MHPMCounterWidth (MHPMCounterWidth ),
.RV32E (RV32E ),
.RV32M (RV32M ),
.RV32B (RV32B ),
.RegFile (RegFile ),
.BranchTargetALU (BranchTargetALU ),
.WritebackStage (WritebackStage ),
.ICache (ICache ),
.ICacheECC (ICacheECC ),
.ICacheTweakInfection (ICacheTweakInfection),
.SecureIbex (SecureIbex ),
.LockstepOffset (LockstepOffset ),
.ICacheScramble (ICacheScramble ),
.BranchPredictor (BranchPredictor ),
.DbgTriggerEn (DbgTriggerEn ),
.DmBaseAddr (DmBaseAddr ),
.DmAddrMask (DmAddrMask ),
.DmHaltAddr (DmHaltAddr ),
.DmExceptionAddr (DmExceptionAddr )

) dut (
.clk_i (clk ),
Expand Down
12 changes: 7 additions & 5 deletions dv/uvm/icache/dv/tb/tb.sv
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Expand Up @@ -4,7 +4,8 @@
//
import ibex_pkg::*;
module tb #(
parameter bit ICacheECC = 1'b1
parameter bit ICacheECC = 1'b1,
parameter bit ICacheTweakInfection = 1'b1
);
// dep packages
import uvm_pkg::*;
Expand Down Expand Up @@ -49,10 +50,11 @@ module tb #(

// DUT
ibex_icache #(
.ICacheECC (ICacheECC),
.BusSizeECC (BusSizeECC),
.TagSizeECC (TagSizeECC),
.LineSizeECC (LineSizeECC)
.ICacheECC (ICacheECC),
.ICacheTweakInfection (ICacheTweakInfection),
.BusSizeECC (BusSizeECC),
.TagSizeECC (TagSizeECC),
.LineSizeECC (LineSizeECC)
) dut (
.clk_i ( clk ),
.rst_ni ( rst_n ),
Expand Down
48 changes: 25 additions & 23 deletions examples/simple_system/rtl/ibex_simple_system.sv
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Expand Up @@ -61,6 +61,7 @@ module ibex_simple_system (
parameter bit ICache = 1'b0;
parameter bit DbgTriggerEn = 1'b0;
parameter bit ICacheECC = 1'b0;
parameter bit ICacheTweakInfection = 1'b0;
parameter bit BranchPredictor = 1'b0;
parameter SRAMInitFile = "";

Expand Down Expand Up @@ -197,29 +198,30 @@ module ibex_simple_system (
end

ibex_top_tracing #(
.SecureIbex ( SecureIbex ),
.LockstepOffset ( LockstepOffset ),
.ICacheScramble ( ICacheScramble ),
.PMPEnable ( PMPEnable ),
.PMPGranularity ( PMPGranularity ),
.PMPNumRegions ( PMPNumRegions ),
.MHPMCounterNum ( MHPMCounterNum ),
.MHPMCounterWidth( MHPMCounterWidth ),
.RV32E ( RV32E ),
.RV32M ( RV32M ),
.RV32B ( RV32B ),
.RV32ZC ( RV32ZC ),
.RegFile ( RegFile ),
.BranchTargetALU ( BranchTargetALU ),
.ICache ( ICache ),
.ICacheECC ( ICacheECC ),
.WritebackStage ( WritebackStage ),
.BranchPredictor ( BranchPredictor ),
.DbgTriggerEn ( DbgTriggerEn ),
.DmBaseAddr ( 32'h00100000 ),
.DmAddrMask ( 32'h00000003 ),
.DmHaltAddr ( 32'h00100000 ),
.DmExceptionAddr ( 32'h00100000 )
.SecureIbex ( SecureIbex ),
.LockstepOffset ( LockstepOffset ),
.ICacheScramble ( ICacheScramble ),
.PMPEnable ( PMPEnable ),
.PMPGranularity ( PMPGranularity ),
.PMPNumRegions ( PMPNumRegions ),
.MHPMCounterNum ( MHPMCounterNum ),
.MHPMCounterWidth ( MHPMCounterWidth ),
.RV32E ( RV32E ),
.RV32M ( RV32M ),
.RV32B ( RV32B ),
.RV32ZC ( RV32ZC ),
.RegFile ( RegFile ),
.BranchTargetALU ( BranchTargetALU ),
.ICache ( ICache ),
.ICacheECC ( ICacheECC ),
.ICacheTweakInfection ( ICacheTweakInfection ),
.WritebackStage ( WritebackStage ),
.BranchPredictor ( BranchPredictor ),
.DbgTriggerEn ( DbgTriggerEn ),
.DmBaseAddr ( 32'h00100000 ),
.DmAddrMask ( 32'h00000003 ),
.DmHaltAddr ( 32'h00100000 ),
.DmExceptionAddr ( 32'h00100000 )
) u_top (
.clk_i (clk_sys),
.rst_ni (rst_sys_n),
Expand Down
34 changes: 18 additions & 16 deletions rtl/ibex_core.sv
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Expand Up @@ -30,6 +30,7 @@ module ibex_core import ibex_pkg::*; #(
parameter bit WritebackStage = 1'b0,
parameter bit ICache = 1'b0,
parameter bit ICacheECC = 1'b0,
parameter bit ICacheTweakInfection = 1'b0,
parameter int unsigned BusSizeECC = BUS_SIZE,
parameter int unsigned TagSizeECC = IC_TAG_SIZE,
parameter int unsigned LineSizeECC = IC_LINE_SIZE,
Expand Down Expand Up @@ -425,22 +426,23 @@ module ibex_core import ibex_pkg::*; #(
//////////////

ibex_if_stage #(
.DmHaltAddr (DmHaltAddr),
.DmExceptionAddr (DmExceptionAddr),
.DummyInstructions(DummyInstructions),
.ICache (ICache),
.RV32ZC (RV32ZC),
.ICacheECC (ICacheECC),
.BusSizeECC (BusSizeECC),
.TagSizeECC (TagSizeECC),
.LineSizeECC (LineSizeECC),
.PCIncrCheck (PCIncrCheck),
.ResetAll (ResetAll),
.RndCnstLfsrSeed (RndCnstLfsrSeed),
.RndCnstLfsrPerm (RndCnstLfsrPerm),
.BranchPredictor (BranchPredictor),
.MemECC (MemECC),
.MemDataWidth (MemDataWidth)
.DmHaltAddr (DmHaltAddr),
.DmExceptionAddr (DmExceptionAddr),
.DummyInstructions (DummyInstructions),
.ICache (ICache),
.RV32ZC (RV32ZC),
.ICacheECC (ICacheECC),
.ICacheTweakInfection (ICacheTweakInfection),
.BusSizeECC (BusSizeECC),
.TagSizeECC (TagSizeECC),
.LineSizeECC (LineSizeECC),
.PCIncrCheck (PCIncrCheck),
.ResetAll (ResetAll),
.RndCnstLfsrSeed (RndCnstLfsrSeed),
.RndCnstLfsrPerm (RndCnstLfsrPerm),
.BranchPredictor (BranchPredictor),
.MemECC (MemECC),
.MemDataWidth (MemDataWidth)
) if_stage_i (
.clk_i (clk_i),
.rst_ni(rst_ni),
Expand Down
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