[top,dv] Init TB top

[martin-velay]

Linked to issue #31, but doesn't cover it all.

Instructions to get the C code running on the top level TB in UVM style:

1. Build the SW with: https://github.com/lowRISC/mocha?tab=readme-ov-file#build
2. Run the simulation with:
   dvsim hw/top_chip/dv/top_chip_sim_cfg.hjson -i uart_smoke -t xcelium
   Result:

UVM_INFO @             20414030: (sw_test_status_if.sv:61) [tb.u_sim_sram.u_sim_sram_if.u_sw_test_status_if] SW test transitioned to SwTestStatusInTest.
...
UVM_INFO @            349734030: (sw_test_status_if.sv:61) [tb.u_sim_sram.u_sim_sram_if.u_sw_test_status_if] SW test transitioned to SwTestStatusPassed.
UVM_INFO @            349734030: (sw_test_status_if.sv:82) [tb.u_sim_sram.u_sim_sram_if.u_sw_test_status_if] ==== SW TEST PASSED ====
...
TEST PASSED CHECKS
 _____         _                                  _ _ 
|_   _|__  ___| |_   _ __   __ _ ___ ___  ___  __| | |
  | |/ _ \/ __| __| | '_ \ / _` / __/ __|/ _ \/ _` | |
  | |  __/\__ \ |_  | |_) | (_| \__ \__ \  __/ (_| |_|
  |_|\___||___/\__| | .__/ \__,_|___/___/\___|\__,_(_)
                    |_|                               

Instructions to get the C code running on the top level TB in Verilator style:

1. Build the SW with: https://github.com/lowRISC/mocha?tab=readme-ov-file#build
2. Build Verilator:
   fusesoc --cores-root=. run --target=sim --tool=verilator --setup --build lowrisc:mocha:top_chip_verilator
3. Run C tests with Verilator:
   ctest --test-dir build/sw -R sim_verilator

Which should give:

Test project /scratch/mvelay/mocha/build/sw
      Start  1: test_framework_test_sim_verilator
 1/14 Test  #1: test_framework_test_sim_verilator ...................   Passed    0.57 sec
      Start  2: test_framework_test_cheri_sim_verilator
 2/14 Test  #2: test_framework_test_cheri_sim_verilator .............   Passed    0.59 sec
      Start  3: test_framework_exception_test_sim_verilator
 3/14 Test  #3: test_framework_exception_test_sim_verilator .........   Passed    0.75 sec
      Start  4: test_framework_exception_test_cheri_sim_verilator
 4/14 Test  #4: test_framework_exception_test_cheri_sim_verilator ...   Passed    0.80 sec
      Start  5: plic_smoketest_sim_verilator
 5/14 Test  #5: plic_smoketest_sim_verilator ........................   Passed    0.47 sec
      Start  6: plic_smoketest_cheri_sim_verilator
 6/14 Test  #6: plic_smoketest_cheri_sim_verilator ..................   Passed    0.53 sec
      Start  7: spi_device_smoketest_sim_verilator
 7/14 Test  #7: spi_device_smoketest_sim_verilator ..................   Passed    1.11 sec
      Start  8: spi_device_smoketest_cheri_sim_verilator
 8/14 Test  #8: spi_device_smoketest_cheri_sim_verilator ............   Passed    1.23 sec
      Start  9: timer_smoketest_sim_verilator
 9/14 Test  #9: timer_smoketest_sim_verilator .......................   Passed    0.48 sec
      Start 10: timer_smoketest_cheri_sim_verilator
10/14 Test #10: timer_smoketest_cheri_sim_verilator .................   Passed    0.54 sec
      Start 11: timer_interrupt_test_sim_verilator
11/14 Test #11: timer_interrupt_test_sim_verilator ..................   Passed    1.19 sec
      Start 12: timer_interrupt_test_cheri_sim_verilator
12/14 Test #12: timer_interrupt_test_cheri_sim_verilator ............   Passed    1.28 sec
      Start 13: uart_smoketest_sim_verilator
13/14 Test #13: uart_smoketest_sim_verilator ........................   Passed    0.46 sec
      Start 14: uart_smoketest_cheri_sim_verilator
14/14 Test #14: uart_smoketest_cheri_sim_verilator ..................   Passed    0.53 sec

100% tests passed, 0 tests failed out of 14

[martin-velay]

@ziuziakowska, I've just pushed all what I had related to the SW-DV topic mentioned in this issue.

[marnovandermaas]

This is some great work! Thanks for learning from Sunburst chip. I've done a code review and left some initial comments.

[martin-velay]

@marnovandermaas, thanks a lot for your good review. I have now taken into account all the comment which required changes. There is only one remaining item: #213 (comment)

Please let me know what you think I should do. If needed we can have a call next week

[martin-velay]

@engdoreis, I have applied the suggested patch. It fixes the UART issue, thanks!

Now, it remains one issue, the CI will fail I believe while running Verilator tests. To fix this I need to change the address below into something else:

mocha/hw/top_chip/dv/verilator/top_chip_verilator.sv

Line 61 in 691dd13

localparam bit [31:0] VERILATOR_SW_DV_START_ADDR = 'h2001_0000;

My suspicion is that this below will trigger a simulation termination:

mocha/hw/top_chip/dv/verilator/top_chip_verilator.sv

Lines 109 to 116 in 691dd13

	always @(posedge clk_i) begin
	if (u_sw_test_status_if.sw_test_done) begin
	$display("Verilator sim termination requested");
	$display("Your simulation wrote to 0x%h", u_sw_test_status_if.sw_test_status_addr);
	dv_test_status_pkg::dv_test_status(u_sw_test_status_if.sw_test_passed);
	$finish;
	end
	end

Anybody knows how to debug this with Verilator? @ziuziakowska or @engdoreis ?

[ziuziakowska]

Locally, I use a script like this called run_verilator.sh that I run with a compiled binary to test:

#!/bin/sh
nix develop --command bash -c "build/lowrisc_mocha_top_chip_system_0/sim-verilator/Vtop_chip_verilator -t -E $1"

So for example, run_verilator.sh build/sw/device/tests/uart_smoketest to run the UART smoketest on Verilator. The -t flag makes the Verilator simulation write out a trace of all the instructions executed to trace_hart_0.dasm in the Mocha directory. The software build also outputs a disassembly of all the compiled binaries, which you can find in build/sw/device/tests/uart_smoketest.dump for that example. Using that disassembly you can find the address of the function that might be causing the issue and following the execution trace. If the tests are failing fast, it is likely that the binaries are running as expected, and the memory write to the unmapped DV status region is trying to proceed as any other write, causing a fault.

You may be able to apply #289 on top of your branch temporarily and try running it with that, as that PR adds printing a register dump on an unhandled exception, so you'll get a view of the registers when the exception occurred printed to the UART (captured in uart0.log).

[martin-velay]

When merging this PR, we'll close issues:

• Improve the verilator uart dpi #192
• Top level DV - Change the interface to sim_sram to comply with the DUT #249
• Top level DV - Add DV_SIM_WINDOW register for CVA6 or a workaround #250
• [verilator] Get rid of the SW magic write to exit the simulation #283
• UART DV - Top-level basic register access #146
• Top level DV - Create a 1st version of the top env with the existing RTL top #31

And it covers half of:

• [SW] Implement DV specific registers to forward log and status #261 (the log part is still missing)

[engdoreis]

I'm happy with the results produced by this PR.

[ziuziakowska]

LGTM on the SW side 👍.

[engdoreis]

The fpga runner error in CI is likely related to my experiments in the runner.

[marnovandermaas]

Thanks for this PR and making CI pass. I've tested the command and it passes.

dvsim hw/top_chip/dv/top_chip_sim_cfg.hjson -i uart_smoke -t xcelium

Let's get this PR merged and we can then build upon it with refinements.

[marnovandermaas]

fpga-test is failing, but the bitstream is building and it's failing on the flashing. This flashing is ok to fail for now as we are still building this CI step.

[martin-velay]

Excellent! I am really happy, thanks all for your support and feedback.