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ot_spi_device: Fix register write issues #240

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Merged
merged 3 commits into from
Oct 17, 2025
Merged

ot_spi_device: Fix register write issues #240

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7176d5c
[ot] hw/opentitan: ot_spi_device: Fix `FLASH_STATUS` writes
AlexJones0 Oct 15, 2025
5b5063a
[ot] hw/opentitan: ot_spi_device: Add missing `ADDR_MODE` reg write
AlexJones0 Oct 15, 2025
9f2c3b5
[ot] tests/opentitan: earlgrey: Add common flaky tests on Earlgrey
AlexJones0 Oct 15, 2025
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33 changes: 20 additions & 13 deletions hw/opentitan/ot_spi_device.c
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Original file line number Diff line number Diff line change
Expand Up @@ -574,17 +574,19 @@ static const char *TPM_REG_NAMES[TPM_REGS_COUNT] = {
#define INTERCEPT_EN_MASK \
(R_INTERCEPT_EN_STATUS_MASK | R_INTERCEPT_EN_JEDEC_MASK | \
R_INTERCEPT_EN_SFDP_MASK | R_INTERCEPT_EN_MBX_MASK)
#define FLASH_STATUS_STATUS_MASK \
(R_FLASH_STATUS_WEL_MASK | R_FLASH_STATUS_BP0_MASK | \
R_FLASH_STATUS_BP1_MASK | R_FLASH_STATUS_BP2_MASK | \
R_FLASH_STATUS_TB_MASK | R_FLASH_STATUS_SEC_MASK | \
R_FLASH_STATUS_SRP0_MASK | R_FLASH_STATUS_SRP1_MASK | \
R_FLASH_STATUS_QE_MASK | R_FLASH_STATUS_LB1_MASK | \
R_FLASH_STATUS_LB2_MASK | R_FLASH_STATUS_LB3_MASK | \
R_FLASH_STATUS_CMP_MASK | R_FLASH_STATUS_SUS_MASK | \
R_FLASH_STATUS_WPS_MASK | R_FLASH_STATUS_DRV0_MASK | \
R_FLASH_STATUS_DRV1_MASK | R_FLASH_STATUS_HOLD_NRST_MASK)
#define FLASH_STATUS_MASK (R_FLASH_STATUS_BUSY_MASK | FLASH_STATUS_STATUS_MASK)
#define FLASH_STATUS_RW0C_MASK \
(R_FLASH_STATUS_BUSY_MASK | R_FLASH_STATUS_WEL_MASK)
#define FLASH_STATUS_RW_MASK \
(R_FLASH_STATUS_BP0_MASK | R_FLASH_STATUS_BP1_MASK | \
R_FLASH_STATUS_BP2_MASK | R_FLASH_STATUS_TB_MASK | \
R_FLASH_STATUS_SEC_MASK | R_FLASH_STATUS_SRP0_MASK | \
R_FLASH_STATUS_SRP1_MASK | R_FLASH_STATUS_QE_MASK | \
R_FLASH_STATUS_LB1_MASK | R_FLASH_STATUS_LB2_MASK | \
R_FLASH_STATUS_LB3_MASK | R_FLASH_STATUS_CMP_MASK | \
R_FLASH_STATUS_SUS_MASK | R_FLASH_STATUS_WPS_MASK | \
R_FLASH_STATUS_DRV0_MASK | R_FLASH_STATUS_DRV1_MASK | \
R_FLASH_STATUS_HOLD_NRST_MASK)
#define FLASH_STATUS_MASK (FLASH_STATUS_RW0C_MASK | FLASH_STATUS_RW_MASK)
#define JEDEC_CC_MASK (R_JEDEC_CC_CC_MASK | R_JEDEC_CC_NUM_CC_MASK)
#define JEDEC_ID_MASK (R_JEDEC_ID_DEVICE_MASK | R_JEDEC_ID_MF_MASK)

Expand Down Expand Up @@ -1633,9 +1635,14 @@ static void ot_spi_device_spi_regs_write(void *opaque, hwaddr addr,
val32 &= INTERCEPT_EN_MASK;
s->spi_regs[reg] = val32;
break;
case R_ADDR_MODE:
s->spi_regs[reg] &= ~R_ADDR_MODE_ADDR_4B_EN_MASK;
s->spi_regs[reg] |= val32 & R_ADDR_MODE_ADDR_4B_EN_MASK; /* RW */
break;
case R_FLASH_STATUS:
s->spi_regs[reg] &= val32 & R_FLASH_STATUS_BUSY_MASK; /* RW0C */
s->spi_regs[reg] |= val32 & FLASH_STATUS_STATUS_MASK; /* RW */
s->spi_regs[reg] &= val32 & FLASH_STATUS_RW0C_MASK; /* RW0C */
s->spi_regs[reg] &= ~FLASH_STATUS_RW_MASK;
s->spi_regs[reg] |= val32 & FLASH_STATUS_RW_MASK; /* RW */
break;
case R_JEDEC_CC:
val32 &= JEDEC_CC_MASK;
Expand Down
20 changes: 10 additions & 10 deletions tests/opentitan/data/earlgrey-tests.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -86,8 +86,8 @@ pass: //sw/device/tests:alert_handler_lpg_reset_toggle_test_sim_qemu_rom_with_fa
pass: //sw/device/tests:alert_handler_lpg_reset_toggle_test_sim_qemu_sival_rom_ext
pass: //sw/device/tests:alert_handler_ping_ok_test_sim_qemu_rom_with_fake_keys
pass: //sw/device/tests:alert_handler_ping_ok_test_sim_qemu_sival_rom_ext
pass: //sw/device/tests:aon_timer_irq_test_sim_qemu_rom_with_fake_keys
pass: //sw/device/tests:aon_timer_irq_test_sim_qemu_sival_rom_ext
flaky: //sw/device/tests:aon_timer_irq_test_sim_qemu_rom_with_fake_keys # Test checks IRQ timing which may be slightly inaccurate on QEMU, and so rarely fails
flaky: //sw/device/tests:aon_timer_irq_test_sim_qemu_sival_rom_ext # Test checks IRQ timing which may be slightly inaccurate on QEMU, and so rarely fails
flaky: //sw/device/tests/autogen:alert_test_sim_qemu_rom_with_fake_keys # Fails rarely when running in parallel on CI runners, likely due to timing issues.
flaky: //sw/device/tests/autogen:alert_test_sim_qemu_sival_rom_ext # Fails rarely when running in parallel on CI runners, likely due to timing issues.
pass: //sw/device/tests:clkmgr_jitter_frequency_test_sim_qemu_rom_with_fake_keys
Expand All @@ -106,10 +106,10 @@ pass: //sw/device/tests:clkmgr_smoketest_sim_qemu_rom_with_fake_keys
pass: //sw/device/tests:clkmgr_smoketest_sim_qemu_sival_rom_ext
pass: //sw/device/tests:crt_test_sim_qemu_rom_with_fake_keys
pass: //sw/device/tests:crt_test_sim_qemu_sival_rom_ext
pass: //sw/device/tests/crypto:aes_functest_sim_qemu_rom_with_fake_keys
pass: //sw/device/tests/crypto:aes_functest_sim_qemu_sival_rom_ext
pass: //sw/device/tests/crypto:aes_gcm_functest_sim_qemu_rom_with_fake_keys
pass: //sw/device/tests/crypto:aes_gcm_functest_sim_qemu_sival_rom_ext
flaky: //sw/device/tests/crypto:aes_functest_sim_qemu_rom_with_fake_keys # Test fails sometimes due to incorrect encrypted data when it didn't before, need to root cause
flaky: //sw/device/tests/crypto:aes_functest_sim_qemu_sival_rom_ext # Test fails sometimes due to incorrect encrypted data when it didn't before, need to root cause
flaky: //sw/device/tests/crypto:aes_gcm_functest_sim_qemu_rom_with_fake_keys # Test fails ~1% of the time due to an illegal instruction exception, need to root cause
flaky: //sw/device/tests/crypto:aes_gcm_functest_sim_qemu_sival_rom_ext # Test fails ~1% of the time due to an illegal instruction exception, need to root cause
flaky: //sw/device/tests/crypto:aes_gcm_timing_test_sim_qemu_rom_with_fake_keys # Passes < 5% of the time. This test checks for constant time crypto operations.
flaky: //sw/device/tests/crypto:aes_gcm_timing_test_sim_qemu_sival_rom_ext # Passes < 5% of the time. This test checks for constant time crypto operations.
pass: //sw/device/tests/crypto:aes_kwp_functest_sim_qemu_rom_with_fake_keys
Expand All @@ -120,8 +120,8 @@ pass: //sw/device/tests/crypto:aes_kwp_sideload_functest_sim_qemu_rom_with_fake_
pass: //sw/device/tests/crypto:aes_kwp_sideload_functest_sim_qemu_sival_rom_ext
pass: //sw/device/tests/crypto:aes_sideload_functest_sim_qemu_rom_with_fake_keys
pass: //sw/device/tests/crypto:aes_sideload_functest_sim_qemu_sival_rom_ext
pass: //sw/device/tests/crypto:drbg_functest_sim_qemu_rom_with_fake_keys
pass: //sw/device/tests/crypto:drbg_functest_sim_qemu_sival_rom_ext
pass: //sw/device/tests/crypto:drbg_functest_sim_qemu_rom_with_fake_keys # Rarely fails entropy randomness check due to lack of key masking
pass: //sw/device/tests/crypto:drbg_functest_sim_qemu_sival_rom_ext # Rarely fails entropy randomness check due to lack of key masking
pass: //sw/device/tests/crypto:ecdh_p256_functest_sim_qemu_rom_with_fake_keys
pass: //sw/device/tests/crypto:ecdh_p256_functest_sim_qemu_sival_rom_ext
pass: //sw/device/tests/crypto:ecdh_p256_sideload_functest_sim_qemu_rom_with_fake_keys
Expand Down Expand Up @@ -182,8 +182,8 @@ pass: //sw/device/tests/crypto:sha384_functest_sim_qemu_rom_with_fake_keys
pass: //sw/device/tests/crypto:sha384_functest_sim_qemu_sival_rom_ext
pass: //sw/device/tests/crypto:sha512_functest_sim_qemu_rom_with_fake_keys
pass: //sw/device/tests/crypto:sha512_functest_sim_qemu_sival_rom_ext
pass: //sw/device/tests/crypto:symmetric_keygen_functest_sim_qemu_rom_with_fake_keys
pass: //sw/device/tests/crypto:symmetric_keygen_functest_sim_qemu_sival_rom_ext
flaky: //sw/device/tests/crypto:symmetric_keygen_functest_sim_qemu_rom_with_fake_keys # Rarely fails entropy randomness check due to lack of key masking
flaky: //sw/device/tests/crypto:symmetric_keygen_functest_sim_qemu_sival_rom_ext # Rarely fails entropy randomness check due to lack of key masking
pass: //sw/device/tests:csrng_kat_test_sim_qemu_rom_with_fake_keys
pass: //sw/device/tests:csrng_kat_test_sim_qemu_sival_rom_ext
pass: //sw/device/tests:csrng_smoketest_sim_qemu_rom_with_fake_keys
Expand Down
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