ot_spi_device: Fix register write issues
#240
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Previously the writes to this register were not correct; the RW0C WEL field was not being included in the write entirely, and the large RW `status` field was just being OR-ed, which is RW1S and not RW, as writing a 0 to a set value bit would not register in the write. Signed-off-by: Alex Jones <alex.jones@lowrisc.org>
The `ADDR_MODE` register was missing from the SPI device's register writes entirely, causing a bad offset error when writing to it. Add this register and implement its single RW `addr_4b_en` field, which must be handled separately to not reset the RO `pending` field in the high bit. Signed-off-by: Alex Jones <alex.jones@lowrisc.org>
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Maybe this PR could also be merged into to this PR: #244 |
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I haven't looked greatly into it but I think that recently a lot of crypto test refactoring / hardening has been merged into upstream Some AES tests seem to be occasionally failing due to incorrect encrypted data being received past a certain point, which is somewhat concerning. This could be because a change upstream has exposed a flaw in QEMU's emulation. I'm marking these flaky for now as well.
I think it is better to leave them separate for now, personally. |
Add tests that I've seen failing rarely in some past CI runs recently. These are failures due to near timing misses (QEMU emulation is not cycle-accurate), randomness quality checks (QEMU uses PRNG and does not implement key masking), and a rare unexpected failure in 1 AES test that needs to be adequately root-caused. Signed-off-by: Alex Jones <alex.jones@lowrisc.org>
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See the commit messages for more details; adds a missing register write and fixes an incorrect one (missing field & incorrect R/W field implementation).