ibex_csr: Fix non-vectored mtvec write behaviour
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AlexJones0
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ibex_csrs: Fix non-vectored mtvec write behaviour ibex_csr: Fix non-vectored mtvec write behaviour
jwnrt
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rivos-eblot
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LGTM but I would copy the comments of the PR into the code itself, as the bit manip seems a bit obsure w/o details :-)
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also here's the RTL reference for how this is tied off in HW: https://github.com/lowRISC/ibex/blob/1f2232a94581538f535f4bb32b2455d8c9beadf1/rtl/ibex_cs_registers.sv#L587-L588 |
This fixes the behaviour of mtvec writes on Ibex to allow writes in non-vectored mtvec encode modes, but always tie the written mode to vectored (mtvec is WARL). This is required for the ECALL RISC-V compliance test to pass in QEMU (as it currently does on FPGA and Silicon targets). Signed-off-by: Alex Jones <alex.jones@lowrisc.org>
Signed-off-by: Alex Jones <alex.jones@lowrisc.org>
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This is needed to allow the
I-ECALL-01RISC-V compliance test to pass as it currently does on FPGA and silicon targets.mtvecis WARL, and in reality will accept writes with invalid encode modes but will just tie them to vectored mode (1).