Skip to content

ibex_csr: Fix non-vectored mtvec write behaviour #268

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 2 commits into from
Oct 30, 2025
Merged

ibex_csr: Fix non-vectored mtvec write behaviour #268

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
2 commits
Select commit Hold shift + click to select a range
7b0dfd1
[ot] target/riscv: ibex_csr: Fix Ibex `mtvec` WARL writes
AlexJones0 Oct 29, 2025
0a962db
[ot] tests/opentitan: earlgrey-tests: Add passing ECALL compliance test
AlexJones0 Oct 30, 2025
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
5 changes: 3 additions & 2 deletions target/riscv/ibex_csr.c
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -113,8 +113,9 @@ static RISCVException write_mtvec(CPURISCVState *env, int csrno,
"CSR_MTVEC: reserved mode not supported 0x" TARGET_FMT_lx
"\n",
val);
/* WARL */
return RISCV_EXCP_NONE;
/* WARL, Ibex will tie any invalid mode writes to 0b01 (vectored) */
val &= ~3u;
val |= 1u;
}

/* bits [7:2] are always 0, address should be aligned in 256 bytes */
Expand Down
2 changes: 2 additions & 0 deletions tests/opentitan/data/earlgrey-tests.txt
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -640,6 +640,8 @@ pass: //third_party/riscv-compliance:I-CSRRWI-01_sim_qemu_rom_with_fake_keys
pass: //third_party/riscv-compliance:I-CSRRWI-01_sim_qemu_sival_rom_ext
pass: //third_party/riscv-compliance:I-DELAY_SLOTS-01_sim_qemu_rom_with_fake_keys
pass: //third_party/riscv-compliance:I-DELAY_SLOTS-01_sim_qemu_sival_rom_ext
pass: //third_party/riscv-compliance:I-ECALL-01_sim_qemu_rom_with_fake_keys
pass: //third_party/riscv-compliance:I-ECALL-01_sim_qemu_sival_rom_ext
pass: //third_party/riscv-compliance:I-ENDIANESS-01_sim_qemu_rom_with_fake_keys
pass: //third_party/riscv-compliance:I-ENDIANESS-01_sim_qemu_sival_rom_ext
pass: //third_party/riscv-compliance:I-IO-01_sim_qemu_rom_with_fake_keys
Expand Down
Loading