ot_earlgrey: Leave hart disabled on reset
#269
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The hart should be disabled on soc reset, and should instead be enabled by the PowerManager when the reset sequence has been properly handled, as the comment suggests. This is already being done correctly on Darjeeling, but is not being done on Earlgrey. Signed-off-by: Alex Jones <alex.jones@lowrisc.org>
jwnrt
approved these changes
Oct 30, 2025
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I did not understand why you would not need As there is no loaded OTP, the Ibex should not start to execute, as LC state is RAW, it would not deliver a signal to the Ibex CPU. This is why Darjeeling needs this option when OTP image is not loaded. I just had a look at the machine configuration for EarlGrey, and here is the culprit: // ot_earlgrey.c:1351
/* remove the following line once LC state is implemented */
IBEX_DEV_BOOL_PROP("lc-ignore", true)In other words, for now, |
This was referenced Oct 30, 2025
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I think this might have just been a small mistake missed in #186 (changes
cs->disabled = 1tocs->disabled = trueon Darjeeling, butcs->disabled = 1tocs->disabled = falseon Earlgrey).The hart should be disabled on soc reset, and should instead be enabled by the PowerManager when the reset sequence has been properly handled, as the comment suggests.
This surprisingly wasn't causing many issues, but when using the debug module I was running into assertion failures surrounding reset sequences where QEMU tried to
reset_exitIbex despite having neverreset_entered it.