lowRISC · loiclefort · Sep 19, 2023 · Sep 6, 2023 · Sep 12, 2023 · Sep 13, 2023
diff --git a/MAINTAINERS b/MAINTAINERS
@@ -1495,7 +1495,7 @@ F: pc-bios/vof*
 RISC-V Machines
 ---------------
 
-Earlgrey OpenTitan platform
+EarlGrey OpenTitan platform
 M: Emmanuel Blot <eblot@rivosinc.com>
 M: Loïc Lefort <loic@rivosinc.com>
 S: Supported

diff --git a/docs/opentitan/checkregs.md b/docs/opentitan/checkregs.md
@@ -42,7 +42,7 @@ options:
 
 ### Examples
 
-* All Earlgrey register files have been copied into `opentitan/regs-251rc1`
+* All EarlGrey register files have been copied into `opentitan/regs-251rc1`
 
   ````sh
   scripts/opentitan/checkregs.py -k -q hw/opentitan ~/opentitan/regs-251rc1/*.h

diff --git a/docs/opentitan/earlgrey.md b/docs/opentitan/earlgrey.md
@@ -1,4 +1,4 @@
-# Earlgrey CW310
+# EarlGrey CW310
 
 ## Supported version
 

diff --git a/docs/opentitan/index.md b/docs/opentitan/index.md
@@ -32,4 +32,4 @@ ninja qemu-img
 ## Supported platforms
 
  * [IbexDemo](ibexdemo.md) built for Digilent Arty7 board
- * [Earlgrey](earlgrey.md) build for CW310 "Bergen" board
+ * [EarlGrey](earlgrey.md) build for CW310 "Bergen" board
diff --git a/hw/opentitan/ot_aes.c b/hw/opentitan/ot_aes.c
@@ -1003,8 +1003,8 @@ static uint64_t ot_aes_read(void *opaque, hwaddr addr, unsigned size)
     case R_DATA_IN_3:
     case R_TRIGGER:
         qemu_log_mask(LOG_GUEST_ERROR,
-                      "W/O register 0x%02" HWADDR_PRIx " (%s)\n", addr,
-                      REG_NAME(reg));
+                      "%s: W/O register 0x%02" HWADDR_PRIx " (%s)\n", __func__,
+                      addr, REG_NAME(reg));
         val32 = 0u;
         break;
     case R_IV_0:
@@ -1085,8 +1085,8 @@ static void ot_aes_write(void *opaque, hwaddr addr, uint64_t val64,
     case R_DATA_OUT_3:
     case R_STATUS:
         qemu_log_mask(LOG_GUEST_ERROR,
-                      "R/O register 0x%02" HWADDR_PRIx " (%s)\n", addr,
-                      REG_NAME(reg));
+                      "%s: R/O register 0x%02" HWADDR_PRIx " (%s)\n", __func__,
+                      addr, REG_NAME(reg));
         break;
     case R_KEY_SHARE0_0:
     case R_KEY_SHARE0_1:

diff --git a/hw/opentitan/ot_csrng.c b/hw/opentitan/ot_csrng.c
@@ -830,7 +830,7 @@ static bool ot_csrng_expedite_uninstantiation(OtCSRNGInstance *inst)
 static void ot_csrng_handle_enable(OtCSRNGState *s)
 {
     /*
-     * As per Earlgrey 2.5.2-rc0:
+     * As per EarlGrey 2.5.2-rc0:
      * "CSRNG may only be enabled if ENTROPY_SRC is enabled. CSRNG may only be
      *  disabled if all EDNs are disabled. Once disabled, CSRNG may only be
      *  re-enabled after ENTROPY_SRC has been disabled and re-enabled."

diff --git a/hw/opentitan/ot_flash.c b/hw/opentitan/ot_flash.c
@@ -297,6 +297,16 @@ REG32(RD_FIFO, 0x1b4u)
      BANK_INFO_PAGE_CFG_SCRAMBLE_EN_MASK | \
      BANK_INFO_PAGE_CFG_ECC_EN_MASK | \
      BANK_INFO_PAGE_CFG_HE_EN_MASK)
+#define MP_REGION_CFG_MASK \
+    (MP_REGION_CFG_RD_EN_MASK | \
+     MP_REGION_CFG_PROG_EN_MASK | \
+     MP_REGION_CFG_ERASE_EN_MASK | \
+     MP_REGION_CFG_SCRAMBLE_EN_MASK | \
+     MP_REGION_CFG_ECC_EN_MASK | \
+     MP_REGION_CFG_HE_EN_MASK)
+#define MP_REGION_MASK \
+     (MP_REGION_BASE_MASK | \
+      MP_REGION_SIZE_MASK)
 #define CONTROL_MASK \
     (R_CONTROL_START_MASK | \
      R_CONTROL_OP_MASK | \
@@ -1157,7 +1167,7 @@ static void ot_flash_regs_write(void *opaque, hwaddr addr, uint64_t val64,
     case R_MP_REGION_CFG_7:
         if (ot_flash_regs_is_wr_enabled(s, reg - R_MP_REGION_CFG_0 +
                                                R_REGION_CFG_REGWEN_0)) {
-            val32 &= BANK_INFO_PAGE_CFG_MASK;
+            val32 &= MP_REGION_CFG_MASK;
             s->regs[reg] = val32;
         }
         break;
@@ -1171,12 +1181,12 @@ static void ot_flash_regs_write(void *opaque, hwaddr addr, uint64_t val64,
     case R_MP_REGION_7:
         if (ot_flash_regs_is_wr_enabled(s, reg - R_MP_REGION_0 +
                                                R_REGION_CFG_REGWEN_0)) {
-            val32 &= BANK_INFO_PAGE_CFG_MASK;
+            val32 &= MP_REGION_MASK;
             s->regs[reg] = val32;
         }
         break;
     case R_DEFAULT_REGION:
-        val32 &= BANK_INFO_PAGE_CFG_MASK;
+        val32 &= MP_REGION_CFG_MASK;
         s->regs[reg] = val32;
         break;
     case R_BANK0_INFO0_PAGE_CFG_0:

diff --git a/hw/opentitan/ot_kmac.c b/hw/opentitan/ot_kmac.c
@@ -1444,12 +1444,7 @@ void ot_kmac_connect_app(OtKMACState *s, unsigned app_idx,
                          const OtKMACAppCfg *cfg, ot_kmac_response_fn fn,
                          void *opaque)
 {
-    if (app_idx >= s->num_app) {
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: Ignoring connection to invalid app index %u\n",
-                      __func__, app_idx);
-        return;
-    }
+    g_assert(app_idx < s->num_app);
 
     OtKMACApp *app = &s->apps[app_idx];
 
@@ -1515,12 +1510,7 @@ static void ot_kmac_start_pending_app(OtKMACState *s)
 void ot_kmac_app_request(OtKMACState *s, unsigned app_idx,
                          const OtKMACAppReq *req)
 {
-    if (app_idx >= s->num_app) {
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: Ignoring connection to invalid app index %u\n",
-                      __func__, app_idx);
-        return;
-    }
+    g_assert(app_idx < s->num_app);
 
     OtKMACApp *app = &s->apps[app_idx];
 
@@ -1609,8 +1599,11 @@ static void ot_kmac_realize(DeviceState *dev, Error **errp)
 {
     OtKMACState *s = OT_KMAC(dev);
 
+    /* make sure num-app property is set */
+    g_assert(s->num_app > 0);
+
     /* make sure we don't overflow pending_apps bitmask */
-    g_assert(s->num_app < 32);
+    g_assert(s->num_app <= 32);
 
     s->apps = g_new0(OtKMACApp, s->num_app);
 }