Initial Sonata XL FPGA build flow#38
Merged
elliotb-lowrisc merged 1 commit intolowRISC:mainfrom Feb 17, 2025
elliotb-lowrisc:fpga
Merged
Initial Sonata XL FPGA build flow#38elliotb-lowrisc merged 1 commit intolowRISC:mainfrom elliotb-lowrisc:fpga
elliotb-lowrisc merged 1 commit intolowRISC:mainfrom
elliotb-lowrisc:fpga
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Nice work Elliot! Haven't been able to test this yet but an initial read-through looks good.
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Add constraints for rst pins of reset synchronisers. Some additional tweaks to instructions. Remove unrelated README tweaks. |
marnovandermaas
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Feb 17, 2025
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Amazing work Elliot, the bitstream built and I see the following output over UART:
Hello from Sonata Chip! 00
Hello from Sonata Chip! 01
Hello from Sonata Chip! 02
Hello from Sonata Chip! 03
Hello from Sonata Chip! 04
Hello from Sonata Chip! 05
Hello from Sonata Chip! 06
Hello from Sonata Chip! 07
Hello from Sonata Chip! 08
Hello from Sonata Chip! 09
Generating pattern
Enabling PWM
Pattgen channel 0 : f0f0f0f0 : aaaaaaaa
PWM output 0 : 00000000 : 00007000
Just a few comments from my end which would be nice to fix before merging. Thanks for your good work here!
New top-level and associated files for basic Sonata XL FPGA dev board support. Primary additions include pin-mapping XDC, Sonata XL-specific clock and reset generation, imported files from sonata-system, and various fusesoc .core files. Software loading currently limited to SRAM init built into the FPGA bitstream.
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New top-level and associated files for basic Sonata XL FPGA dev board support. Primary additions include pin-mapping XDC, Sonata XL-specific clock and reset generation, imported files from sonata-system, and various fusesoc .core files. Software loading currently limited to SRAM init built into the FPGA bitstream.