Spi work (Note: 1 invasive fix) #106
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Signed-off-by: Michael Brown <producer@holotronic.dk>
Signed-off-by: Michael Brown <producer@holotronic.dk>
the-snowwhite
changed the title
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@cdsteinkuehler is obviously away - but I have no idea about the extra clock cycles. Leaving for now. |
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Ok |
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It sounds like the multiple write issue is related to the handshake on the Avalon bus. I always use the wait signal, but the bus can be setup to have a fixed number of wait states and no handshake, which is what I think was causing the apparent 3x writes (one actual write, plus two clocks with the write signals in the same state due to the bus setup). The other changes seem fine, merging. |
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Went thru the build system smoth like butter :-) |
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This adds 2 configs for the DExx_Cramps 1 with bspi and 1 with dbspi (buffered spi with decoded chip selects).
However to get the spi's to not send 3 datastreams for each write I had to change the write timing in the global hm2 uio qsys core(set_interface_property slave writeWaitTime 0):
the-snowwhite@b988a7b#diff-866caa37e2c4e9882a0a92a9672af4ceR147
@cdsteinkuehler
Seems like every time a hm2 core register was written there has been 2 extra writes/clock cycles that so far has gone unnoticed ... ?