This project demonstrates a basic hardware verification environment implemented in Python using Object-Oriented Programming (OOP) principles. It mimics the architecture of modern Universal Verification Methodology (UVM) frameworks used in industry-standard EDA tools.
The script models a hardware testbench environment through three core components:
-
DataPacket (
class DataPacket) — Acts as the UVM Sequence Item. It encapsulates the transaction data (randomized addresses and data payloads) in hexadecimal format. -
PacketGenerator (
class PacketGenerator) — Acts as the UVM Sequencer/Driver. It uses random distribution to generate verification stimulus to stress-test system constraints. -
VerificationMonitor (
class VerificationMonitor) — Acts as the UVM Monitor & Scoreboard. It continuously tracks the generated data packets, checks them against protocol constraints (e.g., maximum valid address limits), flags runtime errors, and logs a test pass/fail summary. -
Ensure you have Python installed, then run the script via your terminal:
python test.py