SecureRISC v1.0.0 — Initial Stable Release

SecureRISC v1.0.0 🔐

First stable release of SecureRISC, a 32-bit RISC-V-style processor with
hardware-assisted security mechanisms implemented at the RTL level.

Highlights

• 32-bit RISC-V-style CPU architecture
• ALU and register file
• Instruction decoder and immediate generator
• Instruction and data memory
• Enhanced instruction verification
• Hardware Memory Protection Unit (MPU)
• Illegal instruction detection and blocking
• Unauthorized memory access detection and blocking
• CPU-level security attack simulation
• Icarus Verilog verification
• GTKWave waveform analysis
• GitHub Actions continuous integration

Verification

• 21/21 instruction verifier tests passed
• 7/7 MPU tests passed
• CPU integration test passed
• Unauthorized memory-write attack blocked
• Security regression passed

Tools

• Verilog
• Icarus Verilog
• GTKWave
• GitHub Actions

Status

SecureRISC v1.0.0 represents the first stable implementation and verification
milestone of the project.

Future work may include FPGA implementation, privilege levels, secure boot,
cryptographic acceleration, formal verification, and hardware-level
security enhancements.