openarch 0.8.0 —— 第四台机器,与第一个部分后端

[Sunrisepeak]

openarch 0.8.0 — a fourth machine, and the first partial backend

The action the trap group was missing

arch_trap_set_handler lets a kernel SEE a trap and
arch_trap_enable_interrupts lets it MASK one. Neither lets it change what the
trap returns to — and that is the whole of preemption, which is the principal
reason to use this layer on a microcontroller.

void arch_trap_switch(arch_trap_frame* f, void* from, void* to);

Called from a handler. It returns normally; the switch happens when the trap
does. Same storage and same arch_context_init as arch_context_switch, so a
task can be resumed by either — the two differ only in WHEN.

⭐⭐ Four machines, four implementations, one name

riscv64 saves mepc across a cooperative switch inside its dispatcher; aarch64
saves ELR_EL1 and SPSR_EL1; x86_64 saves nothing because its iret frame
travels with the stack. Cortex-M does none of that: its handler runs on MSP
while the task runs on PSP, so it pends PendSV and the hardware performs the
switch at exception exit. Three of four share a mechanism; the fourth cannot,
and that is exactly what an interface function earns its place by hiding.

The first PARTIAL backend

openarch-cortex-m declares openarch-backend and openarch:preemption, and
NOT openarch:address-space or openarch:percpu-register: M-profile has a
region-based MPU with no page-table entry to construct, and no TPIDR-class
register. A kernel that needs either is refused BY NAME at resolution rather
than by a wall of undefined reference to arch_pte_* at link time.

Splitting the capability made admitting the machine possible;
openarch:preemption made it worth doing.

Measured

examples/switch on riscv64, aarch64 and x86_64 — each now asserting that a
trap resumed a DIFFERENT context, via a counter the other context advanced.
examples/preempt on mps2-an385 under xim:qemu-arm@9.2.4-1: two tasks that
never yield, each proving it was interrupted, 15 consecutive runs.

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