v1.0.0 - Initial Release

CPLD-FPGA Toolkit v1.0.0

AI-assisted programmable logic design for CPLD and FPGA workflows.

What's included

Skills:

• wincupl-cpld-generation — CUPL source generation, WinCUPL compilation, CSIM simulation
• icestudio-fpga-generation — Verilog generation in iCEstudio .ice projects, synthesis/PnR
• icestudio-fpga-analysis — custom board validation, Verilog AST analysis
• programmable-logic-shared-knowledge — cross-domain design patterns

Knowledge:

• MegaMemory knowledge graph with 180+ verified facts
• 121 Verilog idioms across 13 categories
• 17 CUPL idioms + 20 74xx IC references
• 28 device profiles (GAL16V8 through ATF1508)
• 39 pinout entries across 7 CPLD families
• 91 board definitions from iCEstudio community catalog

Supported devices:

• CPLD: GAL16V8, GAL22V10, ATF750C, ATF1500A, ATF1502, ATF1504, ATF1508, ATF2500C
• FPGA: iCE40 LP/HX/UP5K/UL1K/U4K, Lattice ECP5, Gowin GW1NR/GW1NZ/GW2A/GW5A

Requirements

• GitHub Copilot (VS Code) or Google Antigravity
• Python 3.9+
• MegaMemory MCP (optional, recommended)
• WinCUPL II (for CPLD workflows)
• iCEstudio (for FPGA workflows)
• apio + oss-cad-suite (for FPGA synthesis)

Quick start

git clone https://github.com/michpro/CPLD-FPGA_Toolkit.git