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LoRA W2: packed adapters, merged qkv/gate_up layers, TP slicing, embedding + logits LoRA #278

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LORA-RUNTIME work item W2 from .agents/specs/lora-adapter.md (§ "Non-overlapping work breakdown").

W1 (the CPU punica brick — LoRALayerWeights, BgmvShrink/BgmvExpand/BgmvExpandSlice, AddLoraLinear, single-slice LoRALinear) landed in 1d37f152, gated by test_punica_cpu. W2 is the next slice:

  • PackedLoRALayerWeights (vllm/lora/lora_weights.py:99-282) — pack + per-slice optimize + is_packed.
  • Multi-slice punica add_shrink / add_expand with output_slices and offset_start (vllm/lora/punica_wrapper/punica_cpu.py:166-236), and the multi-slice add_lora_linear (:265-312).
  • The LoRA-wrapped layer family (vllm/lora/layers/): replicated, column-parallel, row-parallel, merged column-parallel (gate_up, 2 slices), QKV (1 slice) and merged QKV (3 slices), with TP slice_lora_a / slice_lora_b including the fully-sharded (S-LoRA) variants.
  • Embedding LoRA (vocal_parallel_embedding.py) via add_lora_embedding, and logits LoRA (logits_processor.py) via add_lora_logits + the vocab_size <= 258048 guard.

Tests: ports tests/lora/test_layers.py (pinned vLLM 555967922) — test_linear_replicated, test_linear_parallel (row/column x fully_shard), test_column_parallel_packed (repeats 1/2/3), test_embeddings, test_lm_head_logits_processor, test_lm_head_logits_processor_invalid_vocab_size.

Out of scope (later Ws in the same spec): metadata/mapping and sgmv segmentation (W3), adapter load/config (W4), the multi-adapter manager (W5), endpoints (W6), GPU punica kernels + fused-MoE packing and the model gate (W7).

Punch-list item 12 (ROAD-V1-D5, headline [H]) in .agents/specs/roadmap-v1-completion.md.

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