Row: SPEC-DFLASH2
Spec: .agents/specs/dflash2-async-spec-sampler.md, wave A2-2. A2-1 landed on main at e64f00560 (#2644), so this wave is next and is blocked on nothing.
What the spec asks for
Split RejectionSampler::forward so the accept walk's outputs stay on device, and give sample_tokens_async a verify arm that routes on exec_state_.step.num_draft_tokens > 0 exactly as sample_tokens already does.
The spec is explicit about what a CPU tier can and cannot prove here: it can gate the routing and the token identity; it cannot gate the overlap. The overlap belongs to G3/G4 at A2-5 and needs dgx:gpu0.
Why the row wants it
async_input_combine_ is vetoed for every speculative engine at both GPUModelRunner constructors, so a spec engine keeps the synchronous host input path. The spec records two independent reasons that veto is load-bearing. A2-1 closed the first one. A2-2 is the wave that closes the second — reason B, that the async sampler has no verify arm at all.
Concretely, a spec step drains the compute stream twice: rejection_sampler.cpp copies the accept walk's results to host and synchronizes, and the DFlash2 speculator downloads the drafted token ids and synchronizes. This wave removes the first.
Measured position
.agents/benchmark-record.md records 0.9280x output throughput against the pinned vLLM (14.951 vs 16.111, GATE_RC=0, 2026-09-02). The gap to parity is 7.2 points. The host-side serialization this chain removes is the largest identified contributor, and no number here may be quoted as a pass — RECORDED, no floor declared is not one.
Out of scope
Flipping the veto (A2-5; the spec says flipping ahead of pieces 1-3 is not a judgement call), A2-3, A2-4, and any change to async_sched_supported_.
Gates
G1 (CPU) as the spec lists: test_mtp_depth, test_dflash2_runner_reach, test_dflash_causality, test_rejection_sampler, test_combine_tokens, test_engine_core_proc, test_runner, green before and after. Plus a red-before test for the routing and for token identity across the split. G3 and G4 are GPU gates belonging to A2-5.
Reachability
If this wave lands unreached while the veto stands, "Nothing lands dead" requires the commit body and PR body to name what is unreached, the owning row, and this issue, and the spec to list it under ## Owed.
Row:
SPEC-DFLASH2Spec:
.agents/specs/dflash2-async-spec-sampler.md, wave A2-2. A2-1 landed onmainate64f00560(#2644), so this wave is next and is blocked on nothing.What the spec asks for
Split
RejectionSampler::forwardso the accept walk's outputs stay on device, and givesample_tokens_asynca verify arm that routes onexec_state_.step.num_draft_tokens > 0exactly assample_tokensalready does.The spec is explicit about what a CPU tier can and cannot prove here: it can gate the routing and the token identity; it cannot gate the overlap. The overlap belongs to G3/G4 at A2-5 and needs
dgx:gpu0.Why the row wants it
async_input_combine_is vetoed for every speculative engine at bothGPUModelRunnerconstructors, so a spec engine keeps the synchronous host input path. The spec records two independent reasons that veto is load-bearing. A2-1 closed the first one. A2-2 is the wave that closes the second — reason B, that the async sampler has no verify arm at all.Concretely, a spec step drains the compute stream twice:
rejection_sampler.cppcopies the accept walk's results to host and synchronizes, and the DFlash2 speculator downloads the drafted token ids and synchronizes. This wave removes the first.Measured position
.agents/benchmark-record.mdrecords 0.9280x output throughput against the pinned vLLM (14.951 vs 16.111,GATE_RC=0, 2026-09-02). The gap to parity is 7.2 points. The host-side serialization this chain removes is the largest identified contributor, and no number here may be quoted as a pass —RECORDED, no floor declaredis not one.Out of scope
Flipping the veto (A2-5; the spec says flipping ahead of pieces 1-3 is not a judgement call), A2-3, A2-4, and any change to
async_sched_supported_.Gates
G1 (CPU) as the spec lists:
test_mtp_depth,test_dflash2_runner_reach,test_dflash_causality,test_rejection_sampler,test_combine_tokens,test_engine_core_proc,test_runner, green before and after. Plus a red-before test for the routing and for token identity across the split. G3 and G4 are GPU gates belonging to A2-5.Reachability
If this wave lands unreached while the veto stands, "Nothing lands dead" requires the commit body and PR body to name what is unreached, the owning row, and this issue, and the spec to list it under
## Owed.