Part of the arm64 port. Only needed for DT platforms without EL3 firmware (enable-method = "spin-table"). Do not build the common path around this.
Where PSCI is absent, a minimal software park is required:
- Host parks a CPU with
cpu_install_idmap() + cpu_soft_restart(el2_switch, park_pa, mailbox_pa, mpidr, 0) (arch/arm64/kernel/cpu-reset.S), the path kexec already uses, including the hyp-stub HVC_SOFT_RESTART handling. Requires the same cpu_hyp_reset() ordering machine_kexec() has.
- Park loop, MMU off, in a host-owned page (~30 instructions): load mailbox, compare MPIDR,
wfe, on match mov x0, dtb; br entry. With the MMU off data accesses are Device-nGnRnE, so no page tables and no cache maintenance in the loop; the writer needs dcache_clean_poc + sev.
- The spawn boots its secondaries with stock
smp_spin_table and a cpu-release-addr pointing at the host-owned mailbox.
- Confirm-parked = the CPU has written its MPIDR into a per-CPU "parked" word.
- No forced halt beyond a plain SGI.
Part of the arm64 port. Only needed for DT platforms without EL3 firmware (
enable-method = "spin-table"). Do not build the common path around this.Where PSCI is absent, a minimal software park is required:
cpu_install_idmap()+cpu_soft_restart(el2_switch, park_pa, mailbox_pa, mpidr, 0)(arch/arm64/kernel/cpu-reset.S), the path kexec already uses, including the hyp-stubHVC_SOFT_RESTARThandling. Requires the samecpu_hyp_reset()orderingmachine_kexec()has.wfe, on matchmov x0, dtb; br entry. With the MMU off data accesses are Device-nGnRnE, so no page tables and no cache maintenance in the loop; the writer needsdcache_clean_poc+sev.smp_spin_tableand acpu-release-addrpointing at the host-owned mailbox.