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Release 0.2.2

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@namazso namazso released this 18 Jan 12:09
· 128 commits to main since this release
0.2.2
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Learn about vigilant mode.

What's Changed

  • Add MSR_IA32_MPERF and MSR_IA32_APERF to allowed MSRs by @DevTechProfile in #44
  • RyzenSMU: Add Z2 Extreme to StrixPoint models by @irusanov in #41
  • AMD: Add CSTATE MSR and allow write to more registers by @irusanov in #45

New Contributors

Full Changelog: 0.2.1...0.2.2

Contributors

irusanov and DevTechProfile
Assets 3
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