1.22.0

This is a major new release with the following changes:

• Added support for evaluating user function calls in Verilog constant expressions (#1518).
• VHDL architectures can now be specified on the command line with -e entity(arch). The previous form entity-arch is still supported.
• Added support for default arguments in Verilog macros.
• Added support for $info, $warning, $error, and $fatal Verilog system tasks.
• Elaboration now supports multiple top level design units (#1588).
• Verilog hierarchical references are now supported.
• External names are now allowed in the prefix of selected or indexed names (#1602, #1603).
• Verilog disable statements are now supported (#1605).
• Added the $tcl_interactive variable to distinguish nvc -i and nvc --do (#1608).
• Added support for VHPI vhpiCbRepAfterDelay callbacks (#1616).
• Several other minor bugs were resolved (#1587, #1594, #1409, #1597, #1599, #1600, #1596, #1569, #1607, #1610, #1590, #1609, #1612, #1606, #1613, #1614, #1595).

Special thank you to @bpadalino, @tmeissner, @Blebowski, @amb5l, @m42uko, @a-panella, @cmarqu, @albydnc, @johonkanen, @augustofg, and Eltvor for sponsoring me!