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docs(design): BufferPool sharding benchmark plan (#1297)#3881

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oferchen merged 1 commit into
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design/buffer-pool-sharding-bench
May 7, 2026
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docs(design): BufferPool sharding benchmark plan (#1297)#3881
oferchen merged 1 commit into
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design/buffer-pool-sharding-bench

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@oferchen oferchen commented May 7, 2026

Summary

  • Adds docs/design/buffer-pool-sharding-bench.md (114 lines) specifying the criterion harness that gates the sharded BufferPool layout from Optimize bandwidth parser ASCII scan #1295.
  • Fixes the bench thread-count grid at 1 / 4 / 16 / 64 with mixed adaptive buffer sizes plus a producer-consumer arm exercising cross-thread asymmetry.
  • Pins pass/fail criteria: linear scaling through 16 threads, >= 2x baseline at 64 threads, no regression below the activation gate, memory ceiling growth <= 30%.
  • Calls out false-sharing on shard cache lines and hot-shard imbalance under nested rayon scopes as the two top risks, with concrete mitigations (CachePadded, per-shard hit-distribution reporting).

Test plan

  • CI fmt + clippy pass on docs-only change.
  • Manual review confirms the document references the correct source line ranges in crates/engine/src/local_copy/buffer_pool/.
  • Implementation work in Optimize bandwidth parser ASCII scan #1295 cites this plan when the bench harness lands.

Specifies the criterion harness that gates the sharded BufferPool
layout from #1295: 1/4/16/64 thread acquire-release loops with mixed
adaptive buffer sizes, pass/fail thresholds keyed to linear scaling
through 16 threads, and explicit risk mitigations for false sharing
and hot-shard imbalance.
@github-actions github-actions Bot added the documentation Improvements or additions to documentation label May 7, 2026
@oferchen oferchen merged commit c7b1eb6 into master May 7, 2026
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@oferchen oferchen deleted the design/buffer-pool-sharding-bench branch May 8, 2026 03:52
oferchen added a commit that referenced this pull request May 18, 2026
Specifies the criterion harness that gates the sharded BufferPool
layout from #1295: 1/4/16/64 thread acquire-release loops with mixed
adaptive buffer sizes, pass/fail thresholds keyed to linear scaling
through 16 threads, and explicit risk mitigations for false sharing
and hot-shard imbalance.
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