FPGA: Switch to default seed 2 to avoid Stratix10 timing failures in the stall_enable sample
#2034
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Signed-off-by: Mendell, Mark P <mark.p.mendell@intel.com>
yuguen
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Nov 7, 2023
yuguen
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stall_enable sample
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Nov 7, 2023
…the stall_enable sample (oneapi-src#2034) This avoids a timing failure on Stratix10 for the default seed
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Existing Sample Changes
Description
This avoids a timing failure on Stratix10 for the default seed
Type of change
How Has This Been Tested?
Generated the makefiles using cmake and looked for -Xsseed=2 argument