ILOGIC / OLOGIC
- IDDR
DDR_CLK_EDGE=SAME_EDGE_PIPELINEDnow supported (fixes #65). - Placed BUFRs are configured and
BUFR_DIVIDEis honoured (PR #151). - MMCM no longer held in reset forever (fixes #79). The RST path is now wired through so an external reset actually deasserts.
- OSERDESE2 emits
IS_CLKDIV_INVERTEDandOSERDES.TRISTATE_WIDTH.W4/IFF.INV_OCLKare configured. IBUFGDSaccepted as an alias ofIBUFDS(fixes #74).- IDDR/ILOGIC fixes: all four IFF flops initialised for an IDDR; no more SRTYPE assert on the combinatorial pass-through; routethru/OSERDES dynamic inversion configured.
- Diff-pair pin errors say which pin is wrong when a pair is constrained backwards (fixes #9).
Memory
- SDP BRAM opposite-side port widths (PR #150). The unused port's width bit is no longer emitted, and 36-wide width markers no longer collide with the other port's width field.
- RAM256X1S mux tree placed in its own slice half (was corrupting the SPO half); RAM128X1S scalar A0..A6 wired into the DRAM control set.
- Registered BRAM outputs emit
ZINV_REGCLKARDRCLK/ZINV_REGCLKB. - SRL cascades place like carry chains, with long chains routed via Q.
Placement & Routing
- LUT6_2 → MUXF7/8/9 use-after-free fixed (PR #148).
- Carry-chain fanout overhaul (PR #134): carry-O fabric fanout relocated, chain splits and sum duplication, spine links and row spread, carry-split livelock fixed.
- Router2 wire reservation is now conflict-aware — fixes the 0.9.x counter-routing failures.
- Final timing analysis runs after router2 (PR #139).
- Heap legaliser robustness: placer1_refine failures propagate instead of hanging, budget-radius growth guard, eviction as last resort, deterministic fallback for sparse site types.
- Slice egress validity and cross-position carry→FF pairings enforced (PR #146).
XDC / Timing
set_multicycle_path -setupsupported in the XDC parser and timing engine.- Combinational loops warn instead of aborting the timing walk.
- XDC diagnostics: warn on target selectors matching nothing (fixes #99),
-quietmode (PR #140), Vivado-stylename[0]one-bit bus ports (fixes #46), IDELAYCTRL with no I/ODELAYs is a warning not an error (fixes #60).
Misc
- FASM output records a run-identity header (PR #153).
- PLLE2
LKTABLE/TABLEprogrammed from PLL-specific tables (PR #138);CLKFBOUT_MULT_Frange-checked instead of crashing (fixes #78). --reportflag for timing + utilization JSON (mainline-style).- CI: per-PR demo-project regression gate; demo bitstreams uploaded as artifacts.
Notable external bumps: prjxray-db to d17fea2 (artix7 ilogic sameedge-pipelined segbits, PR #6) and further artix7/kintex7 HP-bank IOB segbits.