Release Bugfix release · openXC7/nextpnr-xilinx

Regional clocking

BUFIO packed onto the BUFIO_BUFIO bel (PR #157).
Pad-fed BUFIO/BUFR constrained to their dedicated sites — a pad-driven BUFIO goes to the site its pad can reach (PR #168), same for BUFR (PR #170).
Regional clock sinks stay inside their clock region — sinks of a regional buffer can no longer escape it (PR #171).
create_clock constraints propagate through buffers and PLL/MMCM (PR #156).
BUFIO_Yn.IN_USE emitted for placed BUFIOs (PR #167).

FDSE/FDPE: a present-but-undefined INIT param is treated the same as absent (PR #179) — fixes undefined init state on these flops.
SRL16E/SRLC32E INIT now actually reaches the bitstream (PR #185).
CARRY4 O fabric fanout relocated at the chain root when CIN is constant (PR #164).
SLICEM half-tile WEMUX consistency enforced (PR #186).
MMCM/PLL fixes (PR #191): IS_PWRDWN_INVERTED is set when a GND-tied PWRDWN pin is disconnected; MMCM PHASE default fixed; IS_RST_INVERTED set on a disconnected RST.

STARTUPE2 constant-tied control pins are disconnected instead of routed (PR #190).

prjxray-db follows: 6b8695e — BUFRCLK enables and MMCM perfclk rows, spartan7 family expansion (PR #182); e8b8e8e4 — zynq7/spartan7 CLK_HROW BUFG-cascade rows (PR #188).

Reverted the dead TFB route-thru filter cleanup (PR #183). The filter removal exposed placement knife-edges that froze DDR3 designs on silicon (Arty S7-50 LiteX memtest). Reverted to restore the silicon-good state; the cleanup can come back once the placement interaction is understood.