cv32e40p_v1.8.3

What's Changed

• Fix issue found in random tests by @dd-baoshan in #2466
• update prev_is_trap to deassert when exit from exception, irq or debug by @dd-baoshan in #2469
• CV32E40Pv2 RISC-V ISA Formal Verif document and plan adition and README update by @pascalgouedo in #2476
• CV32E40Pv2 test list update. by @pascalgouedo in #2477
• Small fix for run_many script by @XavierAubert in #2470
• Added behavior discussed in Issue 2123 for USE_ISS by @XavierAubert in #2471
• Fix issue found in random test by @dd-baoshan in #2472
• CV32E40Pv2 another case of conflict around compress reg fixed by @XavierAubert in #2473
• Reduced interrupt delay (long scenario) by @XavierAubert in #2478
• Up-to-date version of CV32E40Pv2 RISC-V ISA Formal Verif plan. by @pascalgouedo in #2483
• V2 regression scripts & other updates by @XavierAubert in #2487
• Illegal instruction generator for CV32E40Pv2 by @XavierAubert in #2492
• IDV_CONFIG_MAX_NET_LATENCY_RETIREMENTS increased from 21 to 25 to resolve an imperas model/RTL mismatch. by @pascalgouedo in #2498
• Changed CV_CORE_TAG to final CV32E40P RTL tag. by @pascalgouedo in #2499
• Removed links to internal Dolphin repos and drives. by @pascalgouedo in #2505
• Preparation for cv32e40pv1.8.3 tag by @XavierAubert in #2506

Full Changelog: cv32e40p_v1.8.2...cv32e40p_v1.8.3

cv32e40p_v1.8.2

What's Changed

• CV32E40Pv2 Verification update Week 19 PR by @dd-BeeNee in #2425
• Cv32e40p/dev by @dd-baoshan in #2428
• Add esle clause on assertion by @dd-baoshan in #2431
• Fix tb issues by @dd-baoshan in #2437
• New define to enable ImperasDV model CV32E40P patch. by @pascalgouedo in #2438
• CV32E40P fix for mem stress scenario with compressed instructions by @XavierAubert in #2439
• Add store restore SP for fpu streams when load store with sp is enabled by @dd-baoshan in #2440
• Reverted PR #2440 as it caused fatal error. by @pascalgouedo in #2441
• (Redo) Add store restore SP for fpu streams when load store with sp is enabled by @dd-baoshan in #2443
• Fix issues found in random tests by @dd-baoshan in #2445
• Add 2 waivers for RTL code coverage (condition, for CFG_P_F0) after proven unreachable using Questa Formal by @dd-BeeNee in #2447
• Fix incorrect stack flow during nested irq by @dd-baoshan in #2448
• Corrected a non-expected behavior due to PR2439 by @XavierAubert in #2453
• Fix hwloop covg model corner issue related to irq check by @dd-baoshan in #2449
• Update v2 DvPlan annotation after review. by @dd-BeeNee in #2455
• Add RTL code coverage waiver for some instances in FPU by @dd-BeeNee in #2457
• updated test list & added missing test cases in DV Plans by @XavierAubert in #2459
• Fix issues that found during regression for corner cases by @dd-baoshan in #2456
• Add RTL Code Coverage waivers following confirmation using SLEC app of JasperGold and SiemensEDA QuestaFormal. by @dd-BeeNee in #2461
• Fix issue found in random tests by @dd-baoshan in #2463

Full Changelog: cv32e40p_v1.8.1...cv32e40p_v1.8.2

cv32e40p_v1.8.1

What's Changed

• CV32E40Pv2 Verification update Week 17 PR by @dd-BeeNee in #2417
• CV32E40Pv2 Verification update Week 18 PR by @dd-BeeNee in #2421

Full Changelog: cv32e40p_v1.7.2...cv32e40p_v1.8.1

cv32e40p_v1.7.2

What's Changed

• Incorporate UNSUPPORTED_WITH kludge for VCS by @MikeOpenHWGroup in #2393
• Restore DSim by @MikeOpenHWGroup in #2397
• Remove UNSUPPORTED_WITH workaround for VCS (resolved as of V-2023.12-1) by @MikeOpenHWGroup in #2402
• CV32E40Pv2 Verification update Week 15 by @XavierAubert in #2405
• CV32E40Pv2 Verification update Week 16 PR by @dd-BeeNee in #2414

New Contributors

• @dd-BeeNee made their first contribution in #2414

Full Changelog: cv32e40p_v1.6.0...cv32e40p_v1.7.2

cv32e40p_v1.6.0

What's Changed

• Latest coverage only by @MikeOpenHWGroup in #438
• Add argument to printf of misa check. Enhance misa check for PULP by @GTumbush in #450
• Clarify signoff by @MikeOpenHWGroup in #442
• Remove RUN_INDEX from single tests by @MikeOpenHWGroup in #448
• Move ci_check to bin by @MikeOpenHWGroup in #454
• Multi-core multi-testbench extensions for core-v-verif by @strichmo in #456
• action items from core_v_verif_multi review session by @strichmo in #459
• Add scripts to create a GitHub action that launches a Metrics regression by @aimeepsutton in #458
• Core v verif multi, update Riviera-PRO makefile by @dawidzim in #466
• Update MergeTest.md by @MikeOpenHWGroup in #468
• Merge in core_v_verif_multi branch by @MikeOpenHWGroup in #469
• Fix for metrics-regress on GitHub Action by @MikeOpenHWGroup in #471
• update vcs.mk by @masgia in #473
• Improvements to metrics-regress script by @aimeepsutton in #474
• Squashed commit of Lee's RVVI contribution by @strichmo in #476
• Restore CORE testbench by @MikeOpenHWGroup in #478
• RVVI integration to master by @strichmo in #479
• Clean up and update makefile for Riviera-PRO by @dawidzim in #480
• fix paths for Indago waveform probing by @strichmo in #482
• OBI unrequested gnt coverage fix by @strichmo in #486
• Merge test by @halfdan-dolva in #493
• append mergetest by @silabs-robin in #499
• Add some feature by @silabs-hfegran in #497
• promise of cookies by @silabs-mateilga in #498
• Edit MergeTest.md by @silabs-oivind in #491
• testing merge and email from Metrics by @strichmo in #500
• mergetest by @strichmo in #501
• Minor cleanup by @MikeOpenHWGroup in #502
• Issue #485: Added optional CV_RESULTS output redirection path by @silabs-hfegran in #505
• Issue #484 Added default run index to all test outputs by @silabs-hfegran in #504
• add DSIM_RESULTS to align compile and run directories for corev-dv by @strichmo in #506
• Issue #483: Added current configuration to output path by @silabs-hfegran in #503
• Correct path to library in riviera makefile by @dawidzim in #511
• Updated Riscv-dv to latest hash by @silabs-hfegran in #509
• Removed magic numbers for mm_ram addresses and added a cycle counter by @silabs-mateilga in #510
• Hack mm_ram to support Verilator by @MikeOpenHWGroup in #513
• fix RUN_INDEX for Metrics coverage by @strichmo in #514
• README cleanup by @MikeOpenHWGroup in #515
• fix compliance issues by @strichmo in #517
• corev-dv rand tests issues by @MikeOpenHWGroup in #518
• Added _VCP in riscv_core_setting by @dawidzim in #520
• Typo by @MikeOpenHWGroup in #516
• Add a coremark test case by @silabs-robin in #522
• regression cleanup for branching core-v-verif by @strichmo in #521
• initial cv32e40x testbench by @strichmo in #529
• Embench deployment to Core-v-verif for cv32e40p by @silabs-mateilga in #526
• Fixes to reenable debug_test in ci_check by @silabs-mateilga in #532
• Hotfix: xrun debug by @silabs-hfegran in #528
• Strichmo/pr/cv32e40x xrun tcl debug by @strichmo in #534
• Cv32e40x/merge dev to rel 27 by @strichmo in #536
• Cv32e40x/merge rel to master 1 by @strichmo in #537
• Cv32e40p/merge master to rel 1 by @strichmo in #538
• Cv32e40x/merge master to rel 2 by @strichmo in #539
• Cv32e40x/merge rel to dev 1 by @strichmo in #540
• Cv32e40p/merge rel to dev 1 by @strichmo in #541
• add CV_CORE_PATH for optionally having rtl repo dir symlinked locally by @silabs-robin in #543
• fix check for CV_CORE_PATH undefined by @strichmo in #546
• add temporary tie offs to new signals in 40x dutwrap by @silabs-robin in #545
• update the cv32e40x hash by @silabs-robin in #547
• Create a UVM agent for ISA coverage by @silabs-robin in #533
• Add a makefile for importing the source code in DVT Eclipse IDE by @gabrielrad in #525
• make imperas iss ovpsim selectable at run-time by @strichmo in #548
• disable scheduled regression on the e40p by @strichmo in #550
• Ported EMBench intergration to 40x by @silabs-mateilga in #553
• fix memory leak by allowing transaction FIFO to continuously fill by @strichmo in #555
• improve error log reporting when embench fails by @strichmo in #556
• Xcelium code coverage updates by @strichmo in #557
• Updated readme section on porting with .gitignore details by @silabs-mateilga in #558
• Added WAVES_MEM option for xrun sims by @halfdan-dolva in #562
• Clone RTL before opening DVT by @gabrielrad in #563
• Updating references/bindings in toplevel tb by @silabs-oysteink in #564
• Added a simple cycle count report to dhrystone by @silabs-mateilga in #566
• Integrate disassembler/decoder into ISA coverage model by @silabs-robin in #554
• add parallel switch to cv_regress under VSIF for regression tuning by @strichmo in #567
• Bugfix uvma_isacov GUI=1 by @silabs-robin in #568
• Add a config for single-cycle stalls in mm_ram by @silabs-robin in #569
• Add ability to pass additional args by @gabrielrad in #571
• mm_ram Cycle counter update by @silabs-mateilga in #570
• update RM licensing by @eroom1966 in #573
• enable dpi_dasm for coverage model across all simulators by @strichmo in #574
• Fix REPO, BRANCH and HASH variables by @MikeOpenHWGroup in #579
• Update to README and GitCheats by @MikeOpenHWGroup in #581
• migrate Verification Plans from core-v-docs to core-v-verif by @strichmo in #582
• merge from cv32e40p/dev to cv32e40p/release by @strichmo in #584
• Merge cv32e40x/dev to cv32e40x/release by @strichmo in #583
• add in support for IO memory updating the RM memeory view by @eroom1966 in #580
• Merge release branches to master by @strichmo in #586
• Update Vplan location and template by @MikeOpenHWGroup in #585
• Cv32e40p/merge master to rel 4 by @strichmo in https://github.com...

cv32e40p_v1.0.0

The cv32e40p_v1.0.0 tag is the release of the core-v-verif repository that was used to run the final regressions of the tag of the same name for https://github.com/openhwgroup/cv32e40p. This indicates the "Functional RTL Freeze" version of that core.

This is intended to be a Production Ready release.