The bottom 30-bits of the mcause CSR is spec'ed to be WLRL. The CV32E40P RTL is implemented such that the bits [30:5] are read-only, always zero and bits [4:0] are fully read-write. It is not clear if this is compliant with the ISA because it allows illegal values for the Exception Code field. Specifically, the core logic should never violate the following:
mcause[31] && (mcause[1] || mcause[4] || mcause[5] || mcause[9])
// Supervisor software interrupt , User timer Supervisor timer or Supervisor external interrupt
!mcause[31] && (mcause[8] || mcause[9])
// e-call from U- or S-mode
In addition, software (csr instructions) should not be able to:
- set either or mcause[1], mcause[4], mcause[5] or mcause[9] and mcause[31] in the same write;
- set either or mcause[1], mcause[4], mcause[5] or mcause[9] if mcause[31] is already set;
- set mcause[8] or mcause[9] when clearing mcause[31] in the same write;
- set mcause[8] or mcause[9] if mcause[31] is already clear.
@eroom1966 has raised an issue against the ISA to seek clarification:
riscv/riscv-isa-manual#597
The bottom 30-bits of the
mcauseCSR is spec'ed to be WLRL. The CV32E40P RTL is implemented such that the bits [30:5] are read-only, always zero and bits [4:0] are fully read-write. It is not clear if this is compliant with the ISA because it allows illegal values for the Exception Code field. Specifically, the core logic should never violate the following:In addition, software (csr instructions) should not be able to:
@eroom1966 has raised an issue against the ISA to seek clarification:
riscv/riscv-isa-manual#597