8387381: RISC-V: assert failed with fastdebug build on systems with different core types - #31717
8387381: RISC-V: assert failed with fastdebug build on systems with different core types#31717zifeihan wants to merge 1 commit into
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… build on systems with different core types
zifeihan
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RealFYang
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Looks reasonable.
Here is what I read about the syscall:
struct riscv_hwprobe {
__s64 key;
__u64 value;
};
long sys_riscv_hwprobe(struct riscv_hwprobe *pairs, size_t pair_count,
size_t cpusetsize, cpu_set_t *cpus,
unsigned int flags);
For value-like keys (eg. vendor, arch, impl), the returned value will only be valid if all CPUs in the given set have the same value. Otherwise -1 will be returned.
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Thanks all for the review. |
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Going to push as commit aa17cf5.
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HI, Can you help to review this patch? Thanks!
Here is a crash with a fastdebug build on SpacemiT Key Stone K3, which has different core types.
On systems with different core types, the kernel hwprobe syscall returns (uint64_t)-1 as value for MARCHID/MIMPID when CPUs disagree[1]. RVNonExtFeatureValue uses the same -1 as its internal sentinel (DEFAULT_VALUE), so enable_feature(-1) hits the assert.
SpacemiT Key Stone K3 has X100 (marchid=0x8000000058000002) and A100 (marchid=0x8000000041000002) cores, querying all CPUs gives marchid=-1 and mimpid=-1.
Fix: use a separate bool _enabled flag instead of the sentinel value.
[1] https://docs.kernel.org/arch/riscv/hwprobe.html
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