First release. Digital Design is fully supported; Analog and Mixed-Signal
are planned for future major versions.
HDL Editor - VHDL/Verilog/SystemVerilog syntax highlighting, multi-tab
editor, live GHDL syntax check on save, code intelligence (outline,
auto-complete, Go to Definition, Symbol Search), Find/Replace in Files,
Quick Open.
Simulation & Debug - GHDL (VHDL-2008/1993/2019), Icarus Verilog,
Verilator, auto-generated VCD per run, Watch panel, breakpoints, smart
testbench generator.
Waveform Viewer - built-in VCD parser (no GTKWave needed), truth-table
view, named markers, PNG/CSV export.
Circuit Canvas - drag-and-drop logic gates, wire routing, visual
animation, VCD recording, VHDL/Verilog/PNG export.
RTL View - parses VHDL directly into a full gate-level schematic, no
external tools required.
FPGA Toolchain - Yosys + nextpnr for iCE40 and ECP5, resource usage
report, no vendor lock-in.
Plugin System - drop-in .dll/.so/.dylib loading with a small
documented C API.
Windows installer (NSIS) included below. See CHANGELOG.md for the full feature
list.