feat: rv64 mul mulh divrem#2467
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876pol merged 4 commits intorv64-branchfrom Mar 4, 2026
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jonathanpwang
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Mar 3, 2026
Resolves INT-6322, INT-6338, INT-6339. Summary: - `jal_lui`, `jalr`, and `auipc` submodules of `riscv` have been ported from RV32 to RV64 - All types/structs renamed from `Rv32*` to `Rv64*` (e.g., `Rv32JalLuiCoreAir` → `Rv64JalLuiCoreAir`, `Rv32JalrExecutor` → `Rv64JalrExecutor`) - Operand width changed from `u32`/4 bytes to `u64`/8 bytes throughout (registers, read/write operations) - `Rv64JalrAdapter` and `Rv64RdWriteAdapter`/`Rv64CondRdWriteAdapter` updated for RV64 register width - New `RV64_WORD_NUM_LIMBS` constant (`RV64_REGISTER_NUM_LIMBS / 2 = 4`) introduced for 32-bit sub-word operations within 64-bit registers - Sign/zero extension semantics for 64-bit registers: - **LUI**: sign-extends bit 31 into the upper 32 bits of `rd` - **JAL**: zero-extends `pc + 4` (always fits in 32 bits) into `rd` - **JALR**: zero-extends both `rs1` (low 32 bits used) and `rd` (`pc + 4`) - **AUIPC**: zero-extends `pc + (imm << 12)` into `rd` - Constraints are mostly unchanged, except in `jal_lui` where: - An extra `is_sign_extend` column is added - `BitwiseOperationLookupBus::send_xor(rd[3], 11000000₂, rd[3] + 11000000₂).eval(is_jal)` has been changed to `BitwiseOperationLookupBus::send_range(rd[3] * (4 * is_jal + is_lui), 2 * rd[3] - is_sign_extend * 256).eval(is_jal + is_lui)` (this is valid since `rd[3]` has already been constrained to `[0, 256)`) - Added negative tests for writing to x0 register in both `jal_lui` and `jalr` (transpiler already prevents writing to x0 in `auipc`) - Added upper-byte trace-tamper negative tests (`rd_upper_bytes_trace_tamper_negative_test`, `rs1_upper_bytes_trace_tamper_negative_test`) for `auipc`, `jal_lui`, and `jalr` to verify that the zero/sign-extended upper 4 bytes are properly constrained by the memory bus - Uncommented `jal_lui`, `jalr`, and `auipc` in `lib.rs`; all three fully wired up in `extension/mod.rs`
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Resolves INT-6319.
Summary:
mul,mulh, anddivremsubmodules ofriscvhave been ported from RV32 to RV64Rv32*toRv64*(e.g.,Rv32MultAdapterAir→Rv64MultAdapterAir,Rv32DivRemExecutor→Rv64DivRemExecutor)u32/4 bytes tou64/8 bytes throughout (registers, multiply/divide operations)Rv64MultAdapter(shared by all three submodules) updated for RV64Rv64Mextension fully wired up inextension/mod.rs— executor enum, AIR registration, and chip creation all uncommented and updated (previously empty withimpl_empty_executor!stub)mul,mulh, anddivreminlib.rs