feat: rv64 mul_w divrem_w#2711
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shuklaayush merged 7 commits intorv64-alu-w-shift-wfrom Apr 17, 2026
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Apr 17, 2026
Resolves INT-7500. Summary: - `loadstore` submodule of `riscv` has been ported from RV32 to RV64 - All types/structs renamed from `Rv32*` to `Rv64*` (e.g., `Rv32LoadStoreAdapterAir` → `Rv64LoadStoreAdapterAir`) - Operand width changed from `u32`/4 bytes to `u64`/8 bytes throughout (`RV32_REGISTER_NUM_LIMBS` → `RV64_REGISTER_NUM_LIMBS`, `RV32_*_AS` → `RV64_*_AS`, `rs1_val: u32` → `u64`) + loadstore now handles the `LOADD`, `LOADWU`, and `STORED` opcodes - `Rv64LoadStoreAdapter` updated for RV64 - New constraint added: upper 4 bytes of `rs1_data` must be zero, since this adapter only supports 32-bit memory addresses - `LoadStoreCoreAir` rewritten to use the `Encoder` primitive in place of the ad-hoc `flags: [T; 4]` scheme, since the 30 valid `(opcode, shift)` pairs no longer fit in the old encoding - New `InstructionCase` enum enumerates all 30 cases; `selector: [T; 7]` replaces `flags: [T; 4]` --------- Co-authored-by: claude[bot] <41898282+claude[bot]@users.noreply.github.com> Co-authored-by: Ayush Shukla <shuklaayush@users.noreply.github.com> Co-authored-by: Claude Opus 4.6 <noreply@anthropic.com>
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Resolves INT-6341, INT-6342. Summary: - `mul_w` and `divrem_w` reuse the existing generic core AIRs (`MultiplicationCoreAir<RV64_WORD_NUM_LIMBS, RV64_CELL_BITS>` and `DivRemCoreAir<RV64_WORD_NUM_LIMBS, RV64_CELL_BITS>`) via type aliases, eliminating the need for duplicated core code. - A new `Rv64MultWAdapter` (`mul_w.rs`) bridges 64-bit register memory with the 4-byte core interface: it reads full 8-byte registers but only passes the low 4 bytes to the core, and sign-extends the 4-byte core output back to 8 bytes on write. - The test suite is largely carried over from the original RV32 code and primarily exercises the reused core AIR logic rather than the newly written adapter. --------- Co-authored-by: claude[bot] <41898282+claude[bot]@users.noreply.github.com> Co-authored-by: Ayush Shukla <shuklaayush@users.noreply.github.com> Co-authored-by: Claude Opus 4.6 <noreply@anthropic.com>
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Resolves INT-6341, INT-6342.
Summary:
mul_wanddivrem_wreuse the existing generic core AIRs (MultiplicationCoreAir<RV64_WORD_NUM_LIMBS, RV64_CELL_BITS>andDivRemCoreAir<RV64_WORD_NUM_LIMBS, RV64_CELL_BITS>) via type aliases, eliminating the need for duplicated core code.Rv64MultWAdapter(mul_w.rs) bridges 64-bit register memory with the 4-byte core interface: it reads full 8-byte registers but only passes the low 4 bytes to the core, and sign-extends the 4-byte core output back to 8 bytes on write.