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    • riscv-aia

      Public
      Makefile
      Creative Commons Attribution 4.0 International
      1980290Updated Nov 15, 2024Nov 15, 2024
    • Zilsd (Load/Store Pair for RV32) Fast-Track Extension
      Makefile
      Creative Commons Attribution 4.0 International
      3751Updated Nov 15, 2024Nov 15, 2024
    • RISC-V Instruction Set Manual
      TeX
      Creative Commons Attribution 4.0 International
      6433.7k20115Updated Nov 14, 2024Nov 14, 2024
    • This specification will define the RISC-V privilege ISA extensions required to support Supervisor Domain isolation for multi-tenant security use cases e.g. confidential-computing, trusted platform services, fault isolation and so on.
      Makefile
      Creative Commons Attribution 4.0 International
      164211Updated Nov 14, 2024Nov 14, 2024
    • This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory protection and scalable compartmentalization.
      Python
      Creative Commons Attribution 4.0 International
      2953325Updated Nov 13, 2024Nov 13, 2024
    • Sail RISC-V model
      Coq
      Other
      1674619060Updated Nov 13, 2024Nov 13, 2024
    • learn

      Public
      Tracking RISC-V Actions on Education, Training, Courses, Monitorships, etc.
      Creative Commons Zero v1.0 Universal
      6856900Updated Nov 13, 2024Nov 13, 2024
    • RISC-V Opcodes
      Python
      BSD 3-Clause "New" or "Revised" License
      3036972524Updated Nov 12, 2024Nov 12, 2024
    • Documentation developer guide
      TeX
      Creative Commons Attribution 4.0 International
      308730Updated Nov 11, 2024Nov 11, 2024
    • Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)
      Makefile
      Creative Commons Attribution 4.0 International
      49247403Updated Nov 11, 2024Nov 11, 2024
    • A base container image populated with the dependencies to build the RISC-V Documentation.
      Apache License 2.0
      8904Updated Nov 11, 2024Nov 11, 2024
    • RISC-V Performance Events Specification
      Python
      Creative Commons Attribution 4.0 International
      2451Updated Nov 6, 2024Nov 6, 2024
    • docs-spec-template

      Public template
      Makefile
      Creative Commons Attribution 4.0 International
      192011Updated Nov 6, 2024Nov 6, 2024
    • OpenEmbedded/Yocto layer for RISC-V Architecture
      BitBake
      Other
      140365173Updated Nov 4, 2024Nov 4, 2024
    • Memory Tagging ISA extension that can be used by software to enforce memory tag checks on memory loads and stores
      Makefile
      Creative Commons Attribution 4.0 International
      1740Updated Nov 1, 2024Nov 1, 2024
    • riscv-cfi

      Public
      This specification is integrated into the Priv. and Unpriv. specifications. This repo is no longer maintained. Please refer to the Priv. and Unpriv. specifications at https://github.com/riscv/riscv-isa-manual
      Makefile
      Creative Commons Attribution 4.0 International
      218501Updated Nov 1, 2024Nov 1, 2024
    • The ISA specification for the Zalasr extension.
      Makefile
      Creative Commons Attribution 4.0 International
      1130Updated Oct 31, 2024Oct 31, 2024
    • RISC-V Self-hosted Trace Development Repositoty
      TeX
      Creative Commons Attribution 4.0 International
      643000Updated Oct 30, 2024Oct 30, 2024
    • RISC-V Configuration Structure
      Python
      Creative Commons Attribution 4.0 International
      1737141Updated Oct 30, 2024Oct 30, 2024
    • RISC-V Architecture Profiles
      Makefile
      Creative Commons Attribution 4.0 International
      33118101Updated Oct 28, 2024Oct 28, 2024
    • This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usages associated with profiling and debug.
      Makefile
      Creative Commons Attribution 4.0 International
      41700Updated Oct 24, 2024Oct 24, 2024
    • Working Draft of the RISC-V J Extension Specification
      Makefile
      Creative Commons Attribution 4.0 International
      1716973Updated Oct 16, 2024Oct 16, 2024
    • Creative Commons Attribution 4.0 International
      152532Updated Oct 1, 2024Oct 1, 2024
    • RISC-V Integrated Matrix Development Repository
      TeX
      Creative Commons Attribution 4.0 International
      643500Updated Sep 30, 2024Sep 30, 2024
    • Trigger Delegation Fast-Track Specification
      TeX
      Creative Commons Attribution 4.0 International
      643001Updated Sep 26, 2024Sep 26, 2024
    • Working Draft of the RISC-V Debug Specification Standard
      Python
      Other
      92459546Updated Sep 12, 2024Sep 12, 2024
    • The repo contains the SPMP architectural specification, which includes capabilities like access control of read/write/execute requests by an hart, address matching, encoding of permissions, exceptions for access violation, and support for virtualization.
      TeX
      Creative Commons Attribution 4.0 International
      71121Updated Sep 10, 2024Sep 10, 2024
    • Makefile
      55101Updated Sep 5, 2024Sep 5, 2024
    • RISC-V Double Trap Fast-Track Extension
      Makefile
      Creative Commons Attribution 4.0 International
      31210Updated Aug 23, 2024Aug 23, 2024
    • This task group will propose ISA extension(s) and non-ISA hardware and software interop interfaces to enable routine reuse and composition of a subcategory of custom extensions called composable extensions.
      Makefile
      Creative Commons Attribution 4.0 International
      0210Updated Jul 19, 2024Jul 19, 2024