Defines in header files are not resolved in source files

[zhuguiyuan]

Defines defined in and included from header files are not defined when analyzing source files.

File structure:

.
├── src
│   ├── define.vh
│   └── top.v
└── vide.toml

vide.toml

sources = ["src"]
include_dirs = ["src"]

define.vh

`ifndef __DEFINE_VH__
`define __DEFINE_VH__

`define SOMETHING

`endif // __DEFINE_VH__

top.v

`include "define.vh"
module top (
    input  wire clk_i,
    input  wire d_i,
    output wire q_o
);

reg q = 0;

`ifdef SOMETHING
  always @(posedge clk_i) q <= ~d_i;
`else
  always @(posedge clk_i) q <= d_i;
`endif

assign q_o = q;

endmodule