Rel 4.13.0.3 #459
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Rel 4.13.0.3 #459
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Writing 0 to MSR IA32_BIOS_SIGN_ID before fetching this MSRs content is required. This is how things are done in cpu/intel/microcode/microcode.c. The "Intel® 64 and IA-32 Architectures Software Developer’s Manual" also recommends this: "It is recommended that this field be preloaded with 0 prior to executing CPUID" (this field being %edx). Change-Id: I24a87aff9a699ed8ab2598007c8b8562d0555ac5 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49670 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
BUG=None BRANCH=dedede TEST=enable CHROMEOS_WIFI_SAR in config of coreboot, emerge-dedede coreboot-private-files-baseboard-dedede coreboot chromeos-bootimage. Cq-Depend: chrome-internal:3531583 Change-Id: If69258db257353c9b859a27e2a4c088f74b00ab9 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49466 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change enables LTE modem for sasuke. - Add LTE modem device into devicetree - Add GPIO control for LTE modem power on and off BUG=177177967 TEST=Built and verified modem device existence with lsusb Change-Id: I34ba8ab00b73f24d1786ab014e9981b172a63a27 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49163 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Create the sasukette variant of the waddledee reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:175848514 BRANCH=None TEST=util/abuild/abuild -p none -t google/dedede -x -a make sure the build includes GOOGLE_SASUKETTE Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com> Change-Id: I0a554efe0919dc2f5880f0f7817a37bd4be88ed9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49456 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Xuxin Xiong <xuxinxiong@huaqin.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
The SoC code has in implicit dependency on this option, so select it in the SoC code instead of the mainboard code. Change-Id: Iea908c142f4a94a107cf74a31d9f5e29668d4b5b Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49667 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
In order to use the function smbios_mainboard_version()
to query the board revision from the EC.
we need to select GOOGLE_SMBIOS_MAINBOARD_VERSION.
BUG=b:177818769
TEST=1. emerge-volteer coreboot chromeos-bootimage
2. flash the image to the device and check board rev
by using command `dmidecode -t 1 | grep Version`
Change-Id: I2474ee03845356d0775f6da25274f696ad33f935
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49644
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Struct will be synced with picasso with followups. Change-Id: I5f460cc3849bf1fad1f6da61169893488ccb2b40 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48855 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Change-Id: I673f038b4ce3c4141db128a65be71e7a242dfd28 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48856 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia27bc256376c61a7330196a5b4a331dd79386fb6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49472 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Chrome EC dropped strago support, so we need to disable it here before updating our Chrome EC submodule. Change-Id: Ied8905e995fd040b981ce18e95e225ade496d23c Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48216 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This cosmetic change does 2 things: - change bitwise shifting to division - Make the division by / KiB explicit for fixed legacy ranges like 0xa0000-0xbffff. Change-Id: If4e05f496abc05e06a944b244824376f3937a57b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49621 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Fixed resources should not overlap. Change-Id: I7a70f5475c1d701db2cb8cbea659bacf6d0c52ae Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49622 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This pulls in the following changes: * Drop geode_lx * cpu/amd/model_fxx: Drop unused microcode * cpu/amd/model_10xx: Drop unused microcode * soc/mediatek/mt8192: Add dram.elf for DRAM full calibration * soc/mediatek/mt8192: Add dpm binary * soc/mediatek/mt8192: Add 4266Mbps flag for dpm & dram blob * soc/mediatek/mt8192: add SPM firmware * soc/mediatek/mt8192: Support 26M clock off in SPM * soc/mediatek/mt8192: Add SSPM firmware * soc/mediatek/mt8192: Add MCUPM firmware * soc/mediatek/mt8192: Update MCUPM firmware * soc/mediatek/mt8192: Support discrete DRAM modules * mb/amd/majolica: Add APCB configuration files Change-Id: I5c18349307421707fac71f392b785f3e2bef3acb Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49675 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This cosmetic change does 2 things: - change bitwise shifting to division - Make the division by / KiB explicit for fixed legacy ranges like 0xa0000-0xbffff. Change-Id: I626989fa6625e0b3613a11e709c614d40a788b0e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49623 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This memory is used for option roms and BIOS. This matches the ACPI code. Change-Id: I53dd4b967569889108352ca70086a12ce252e8e0 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49624 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This cosmetic change does 2 things: - change bitwise shifting to division - Make the division by / KiB explicit for fixed legacy ranges like 0xa0000. Change-Id: Ia6c2ee29e37040ea9b11505e9888c7f6f8da78bc Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49625 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Fixed resources should not overlap. Change-Id: I166e0095ac0cc0dd8271a693bb452f505a1a9413 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49626 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The BACKLIGHT_ENABLE pin on this board unfortunately defaults to a pull-up on power on, meaning the backlight is immediately enabled. Best we can do about that is to turn it off again early and wait until it is actually correct in the panel power sequence to turn it back on. Some panels want an explicit 80ms delay after training the eDP connection before the backlight is turned on (this is probably just to avoid temporary display artifacts, but whatever). We don't want to busy-wait that extra time, so instead just delegate turning on that GPIO to the payload (which is also in charge of the backlight PWM already). Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Id8dafbdcb40175fbc9205276eee698583b971873 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49495 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Douglas Anderson <dianders@chromium.org>
Only amd/picasso and amd/stoneyridge have reference to PCNT and that could be replaced with acpigen. Remove the PCNT name from GNVS OperationRegion elsewhere. Change-Id: I7dd45a840b3585fd24c31fd923b991c34ab4d783 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49272 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
APIC was not referenced anywhere in ASL. MPEN has references under boards: getac/p470, roda/rk9, roda/rk886ex. MPEN has reference also in Intel SpeedStep ASL. Replace static MPEN with detection of multiple CPUs installed. Change-Id: Ib5f06416b23196b7227ccd5814162925c31c084b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49273 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Functionality depends of CMAP and CMBP references inside board specific ASL implementation. Only roda/rk9 and roda/rk886ex has that. Change-Id: I4da8292375cb589d67dc68496b1e81971bc2a61f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49274 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Change-Id: Iaa05c1162b2533957091c719ea43ffb8d004c5eb Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49275 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Until now some FSP-S parameters were configured for Siemens APL mainboards via the Binary Configuration Tool (BCT). For simplification, the original APL FSP binary should now be used. For this purpose, the corresponding FSP-S parameters are set via devicetree, respectively via mainboard_silicon_init_params accordingly. The following parameters are affected: - Disable CPU power states (C-states) - Set lowest Max Pkg Cstate - PkgC0C1 - Disable PCIe Hot Plug for all enabled RPs - Disable PCIe Transmitter Half Swing for all RPs - Disable PCIe Active State Power Management (ASPM) for all RPs - Disable PCIe L1 Substates for all RPs TEST: - Compare old with new coreboot log on mc_apl5, found no differences - Boot Linux v4.4 and check output of 'lspci' Change-Id: I5af627defd6426140cc9a74bb18db400a8971d72 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49462 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Add scp voltage initialization. BUG=none BRANCH=none TEST=boot asurada correctly Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Change-Id: I68302715ae804fed11bb54f4dfc4e90cde5224df Reviewed-on: https://review.coreboot.org/c/coreboot/+/49355 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
We need to write some special values to key protection registers before applying init_setting table and lp_setting table to PMIC. Otherwise, those settings won't take effect. After applying init_setting table and lp_setting table, we lock the settings by writing zero to key protection registers. Reference datasheet: MT6359_PMIC_Data_Sheet_V1.5.docx, RH-D-2018-0205. BUG=b:172636735 BRANCH=none TEST=boot asurada correctly Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Change-Id: I593d4e02bf0b62ac297957caf4ae1c1837f1f38d Reviewed-on: https://review.coreboot.org/c/coreboot/+/48954 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Change-Id: Ied235972d24276d7c88a2f50f192d69d24ae6e05 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45816 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Do early pad configuration in early bootblock before console init, to make the console work as early as possible. The board does not do any other gpio configuration in bootblock, so this should not influence behaviour in a negative way (e.g. breaking overrides). Change-Id: I342b9217af0288a3b525e629aac791eb0f880442 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49420 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
Do early pad configuration in early bootblock before console init, to make the console work as early as possible. The board does not do any other gpio configuration in bootblock, so this should not influence behaviour in a negative way (e.g. breaking overrides). Change-Id: I67bdd9a96928b77a9a178afea7dab03dc370312c Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49421 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
Do early pad configuration in early bootblock before console init, to make the console work as early as possible. The board does not do any other gpio configuration in bootblock, so this should not influence behaviour in a negative way (e.g. breaking overrides). Change-Id: I2f484d232a46214ff98168f41f96d56b047892e2 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49422 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
Do early pad configuration in early bootblock before console init, to make the console work as early as possible. The board does not do any other gpio configuration in bootblock, so this should not influence behaviour in a negative way (e.g. breaking overrides). Change-Id: I795b8da3c5e1efb51c8fe4673f025839a1c630bc Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49423 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
Change-Id: Iab19538e1f5a74b714cb2a34855d9717315b9018 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49884 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Singer <felixsinger@posteo.net>
Based on reference code, update the DMI ASPM setup steps. Change-Id: I1248305b2f76f48f4e6910de1a6980e942f16945 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48536 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reference code does not run any DMI recipe for Sandy Bridge. Create a helper function and exit early for Sandy Bridge. The CPUID value will be used in a follow-up, since DMI setup has stepping-specific steps. Change-Id: I5d7afb1ef516f447b4988dd5c2f0295771d5888e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48413 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Signed-off-by: Idwer Vollering <vidwer@gmail.com> Change-Id: I4523b1b235064f89c01530b47c9cb4c3c11c9761 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49306 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
non-linux OSes Signed-off-by: Idwer Vollering <vidwer@gmail.com> Change-Id: Iba50d8a8609eda974f12b0d9802e04d7371aed5b Reviewed-on: https://review.coreboot.org/c/coreboot/+/49307 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
…nux OSes Signed-off-by: Idwer Vollering <vidwer@gmail.com> Change-Id: I763b0e7c7c81a2447ed20db0a25047d106e30606 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49308 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Signed-off-by: Idwer Vollering <vidwer@gmail.com> Change-Id: I8d9493ce0c3fa97ea9c3c2f60a0106bb98bd8315 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49309 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Built google/auron (Lulu) provides identical 'dsdt.dsl' files. Change-Id: I5728b220e88d4105fcf6e5cee78662bc80fa01d7 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46169 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
All callsites of `rmw_1d0` use the same `flag` value. Change-Id: I84fab5d3fd270ce684cd6ca892c213b0d8610283 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49578 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Add UPDs for edp phy tuning adjust. BUG=b:171269338 BRANCH=zork TEST=Build, verify the parameter pass to picasso-fsp Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: I389bc4b5726f70bb1edfd858dba1c575cf68050b Reviewed-on: https://review.coreboot.org/c/coreboot/+/48733 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
needs to adjust the eDP phy setting to fix the eDP noise for WWAN. DP_VS_LEVEL0_PREEMPH_LEVEL0, = 0x00 (0.4v 0db) swing 0, pre-emphasis 0) COMMON_MAR_DEEMPH_NOM = 0x004B COMMON_SELDEEMPH60 = 0x0 CMD_BUS_GLOBAL_FOR_TX_LANE0 = 0x80 BUG=b:171269338 BRANCH=none TEST=Build; Verify the UPD was passed to system integrated table Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: Ibe720e26d2257e05a989eaa1fd85d542005cf6a6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48734 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add UPDs for eDP power sequence adjust. BUG=b:171954512 BRANCH=zork TEST=Build, verify the parameter pass to picasso-fsp Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: Ic4bafd86ffb7804c4739f9d30beb67549b71d289 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48863 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Add UPDs for eDP power sequence adjust all pwr sequence numbers below are in uint of 4ms. BUG=b:171269338 TEST=Build; Verify the UPD was pass to system integrated table; measure the power on sequence on dalboz Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: I6eceebd1c3f522e6a8dfaadc487a590107ae3131 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48864 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
set pwron_varybl_to_blon to 0x5, which means fw will delay 20ms between backlight on and vary backlight. BUG=b:171269338 BRANCH=zork TEST=Build; Verify the UPD was passed to system integrated table; measure the power on sequence on dalboz Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: I8af35eee7777a8e71b42f0c128795290b8c2c93e Reviewed-on: https://review.coreboot.org/c/coreboot/+/48865 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Declare the following panel for Katsu: - BOE_TV105WUM_NW0 - STA_2081101QFH032011_53G BUG=b:176523929 TEST=build Katsu image passed BRANCH=kukui Change-Id: I59a02198bc0e13f2760677ae4ea3eb05eb883464 Signed-off-by: chenzanxi <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49830 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
For board version 6 afterward, it will have external pull-up for GPP_C12, and remove internal pull-up. BUG=b:177618684 TEST=emerge-dedede coreboot, check evtest if SW_PEN_INSERTED event (value:1/0) when insert/eject pen, and eject pen to wake system from s0ix Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Change-Id: I503873afb48384168dcd8a822c7246655898356e Reviewed-on: https://review.coreboot.org/c/coreboot/+/49469 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Henry Sun <henrysun@google.com>
Signed-off-by: Marek Kasiewicz <marek.kasiewicz@3mdeb.com>
miczyg1
reviewed
Jan 25, 2021
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@Sakoram tried to run built binaries on apu1 and apu2? |
added 2 commits
January 26, 2021 10:36
Signed-off-by: Marek Kasiewicz <marek.kasiewicz@3mdeb.com>
Signed-off-by: Marek Kasiewicz <marek.kasiewicz@3mdeb.com>
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Yes, they boots. |
Member
|
@Sakoram great. I will merge it now and place a tag tomorrow |
miczyg1
approved these changes
Jan 26, 2021
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